KEYMGR Simulation Results

Wednesday April 09 2025 20:18:57 UTC

GitHub Revision: 96c9c77

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.850s	135.843us	1	1	100.00
V1	random	keymgr_random	3.390s	48.601us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.160s	123.020us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.670s	4.300us	0	1	0.00
V1	csr_bit_bash	keymgr_csr_bit_bash	10.580s	856.324us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	4.740s	68.784us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.250s	22.996us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.670s	4.300us	0	1	0.00
		keymgr_csr_aliasing	4.740s	68.784us	1	1	100.00
V1		TOTAL			6	7	85.71
V2	cfgen_during_op	keymgr_cfg_regwen	40.510s	1.183ms	1	1	100.00
V2	sideload	keymgr_sideload	3.360s	315.836us	1	1	100.00
		keymgr_sideload_kmac	3.860s	107.024us	1	1	100.00
		keymgr_sideload_aes	26.310s	7.084ms	1	1	100.00
		keymgr_sideload_otbn	3.460s	89.435us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.510s	42.476us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	2.840s	249.785us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.270s	259.298us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	3.530s	389.852us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	6.580s	808.324us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.830s	79.297us	1	1	100.00
V2	stress_all	keymgr_stress_all	44.740s	2.681ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.770s	9.103us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.800s	12.497us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.690s	548.515us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.690s	548.515us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.160s	123.020us	1	1	100.00
		keymgr_csr_rw	1.670s	4.300us	0	1	0.00
		keymgr_csr_aliasing	4.740s	68.784us	1	1	100.00
		keymgr_same_csr_outstanding	2.480s	43.850us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.160s	123.020us	1	1	100.00
		keymgr_csr_rw	1.670s	4.300us	0	1	0.00
		keymgr_csr_aliasing	4.740s	68.784us	1	1	100.00
		keymgr_same_csr_outstanding	2.480s	43.850us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	4.800s	262.650us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	4.800s	262.650us	1	1	100.00
		keymgr_tl_intg_err	3.580s	202.383us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	3.850s	388.661us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	3.850s	388.661us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	3.850s	388.661us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	3.850s	388.661us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	4.260s	184.935us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	4.800s	262.650us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	4.800s	262.650us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	3.580s	202.383us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	3.850s	388.661us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	40.510s	1.183ms	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	3.390s	48.601us	1	1	100.00
		keymgr_csr_rw	1.670s	4.300us	0	1	0.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	3.390s	48.601us	1	1	100.00
		keymgr_csr_rw	1.670s	4.300us	0	1	0.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	3.390s	48.601us	1	1	100.00
		keymgr_csr_rw	1.670s	4.300us	0	1	0.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	2.840s	249.785us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	6.580s	808.324us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	6.580s	808.324us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	3.390s	48.601us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.240s	77.719us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	4.800s	262.650us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	4.800s	262.650us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	4.800s	262.650us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	6.080s	380.372us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	2.840s	249.785us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	4.800s	262.650us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	4.800s	262.650us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	4.800s	262.650us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	6.080s	380.372us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	6.080s	380.372us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	4.800s	262.650us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	6.080s	380.372us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	4.800s	262.650us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	6.080s	380.372us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	10.360s	599.104us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	30	96.67

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test keymgr_csr_rw has 1 failures.

    • 0.keymgr_csr_rw.39265860359104216418309149489812783390124965187324806619508146343501526571184
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[13] & 'hffffffff)))'
        UVM_ERROR @   4299775 ps: (keymgr_csr_assert_fpv.sv:431) [ASSERT FAILED] attest_sw_binding_0_rd_A
        UVM_INFO @   4299775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---