KMAC/MASKED Simulation Results

Wednesday April 09 2025 20:18:57 UTC

GitHub Revision: 96c9c77

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	49.280s	3.207ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.800s	50.419us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.580s	19.931us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	14.510s	2.996ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.000s	1.795ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.100s	103.006us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.580s	19.931us	1	1	100.00
		kmac_csr_aliasing	7.000s	1.795ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.500s	10.364us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.840s	39.581us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	32.226m	90.614ms	1	1	100.00
V2	burst_write	kmac_burst_write	9.863m	32.073ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	34.324m	578.801ms	1	1	100.00
		kmac_test_vectors_sha3_256	39.370s	33.266ms	1	1	100.00
		kmac_test_vectors_sha3_384	23.101m	53.517ms	1	1	100.00
		kmac_test_vectors_sha3_512	15.444m	39.747ms	1	1	100.00
		kmac_test_vectors_shake_128	3.969m	253.965ms	1	1	100.00
		kmac_test_vectors_shake_256	28.500m	221.430ms	1	1	100.00
		kmac_test_vectors_kmac	2.080s	53.542us	0	1	0.00
		kmac_test_vectors_kmac_xof	3.460s	447.169us	1	1	100.00
V2	sideload	kmac_sideload	1.106m	9.572ms	1	1	100.00
V2	app	kmac_app	2.136m	2.870ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.864m	67.476ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	4.737m	33.491ms	1	1	100.00
V2	error	kmac_error	2.205m	32.078ms	1	1	100.00
V2	key_error	kmac_key_error	6.320s	1.807ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	8.760s	1.362ms	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.740s	15.650us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.780s	25.499us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	12.480s	6.242ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.190s	44.246us	1	1	100.00
V2	stress_all	kmac_stress_all	14.019m	11.779ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.630s	22.639us	1	1	100.00
V2	alert_test	kmac_alert_test	1.580s	13.805us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.500s	49.538us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.500s	49.538us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.800s	50.419us	1	1	100.00
		kmac_csr_rw	1.580s	19.931us	1	1	100.00
		kmac_csr_aliasing	7.000s	1.795ms	1	1	100.00
		kmac_same_csr_outstanding	2.490s	96.110us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.800s	50.419us	1	1	100.00
		kmac_csr_rw	1.580s	19.931us	1	1	100.00
		kmac_csr_aliasing	7.000s	1.795ms	1	1	100.00
		kmac_same_csr_outstanding	2.490s	96.110us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.890s	51.415us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.890s	51.415us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.890s	51.415us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.890s	51.415us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.140s	154.722us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	39.450s	8.407ms	1	1	100.00
		kmac_tl_intg_err	3.760s	407.729us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.760s	407.729us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.190s	44.246us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	49.280s	3.207ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.106m	9.572ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.890s	51.415us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	39.450s	8.407ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	39.450s	8.407ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	39.450s	8.407ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	49.280s	3.207ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.190s	44.246us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	39.450s	8.407ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.583m	8.144ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	49.280s	3.207ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.250s	35.085us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			37	40	92.50

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:

  • Test kmac_test_vectors_kmac has 1 failures.

    • 0.kmac_test_vectors_kmac.62891508513077795567696711638901356888918731047563572128421826257709428980527
      Line 73, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_test_vectors_kmac/latest/run.log

        UVM_ERROR @  53541855 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @  53541855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.8871183318291908491851257501795565863159364764567903331119239059084278127961
      Line 80, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  35084563 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
        UVM_INFO @  35084563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.18714790806654294143906001459448558740065357230015557297914364045515598824888
      Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[39] & 'hffffffff)))'
        UVM_ERROR @ 154722023 ps: (kmac_csr_assert_fpv.sv:492) [ASSERT FAILED] prefix_0_rd_A
        UVM_INFO @ 154722023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---