KMAC/UNMASKED Simulation Results

Wednesday April 09 2025 20:18:57 UTC

GitHub Revision: 96c9c77

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	43.330s	5.490ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.730s	76.682us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.580s	17.461us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.090s	575.443us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.510s	196.470us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.160s	65.873us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.580s	17.461us	1	1	100.00
		kmac_csr_aliasing	4.510s	196.470us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.510s	32.769us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.860s	60.927us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	15.919m	205.113ms	1	1	100.00
V2	burst_write	kmac_burst_write	1.307m	30.657ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	25.565m	188.014ms	1	1	100.00
		kmac_test_vectors_sha3_256	25.780s	3.456ms	1	1	100.00
		kmac_test_vectors_sha3_384	16.260s	1.687ms	1	1	100.00
		kmac_test_vectors_sha3_512	8.579m	19.326ms	1	1	100.00
		kmac_test_vectors_shake_128	27.355m	74.138ms	1	1	100.00
		kmac_test_vectors_shake_256	25.067m	166.326ms	1	1	100.00
		kmac_test_vectors_kmac	3.020s	262.761us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.920s	151.318us	1	1	100.00
V2	sideload	kmac_sideload	2.127m	2.422ms	1	1	100.00
V2	app	kmac_app	1.633m	7.530ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	13.940s	539.595us	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.531m	33.672ms	1	1	100.00
V2	error	kmac_error	2.472m	2.999ms	1	1	100.00
V2	key_error	kmac_key_error	5.690s	2.090ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.910s	232.542us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	29.180s	9.946ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	16.430s	438.049us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	10.690s	1.274ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.110s	71.780us	1	1	100.00
V2	stress_all	kmac_stress_all	26.987m	131.565ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.730s	20.516us	1	1	100.00
V2	alert_test	kmac_alert_test	1.710s	19.116us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.130s	365.851us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.130s	365.851us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.730s	76.682us	1	1	100.00
		kmac_csr_rw	1.580s	17.461us	1	1	100.00
		kmac_csr_aliasing	4.510s	196.470us	1	1	100.00
		kmac_same_csr_outstanding	2.260s	57.500us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.730s	76.682us	1	1	100.00
		kmac_csr_rw	1.580s	17.461us	1	1	100.00
		kmac_csr_aliasing	4.510s	196.470us	1	1	100.00
		kmac_same_csr_outstanding	2.260s	57.500us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.500s	74.412us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.500s	74.412us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.500s	74.412us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.500s	74.412us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.500s	320.137us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	23.990s	2.326ms	1	1	100.00
		kmac_tl_intg_err	3.570s	183.404us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.570s	183.404us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.110s	71.780us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	43.330s	5.490ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	2.127m	2.422ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.500s	74.412us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	23.990s	2.326ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	23.990s	2.326ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	23.990s	2.326ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	43.330s	5.490ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.110s	71.780us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	23.990s	2.326ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	59.020s	3.094ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	43.330s	5.490ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	37.840s	20.605ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.41278377019764475566690847717569745250075692610375949541058542992006083733055
      Line 149, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 20605296325 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 20605296325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---