OTBN Simulation Results

Wednesday April 09 2025 20:18:57 UTC

GitHub Revision: 96c9c77

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	120.946us	1	1	100.00
V1	single_binary	otbn_single	8.000s	19.510us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	39.667us	1	1	100.00
V1	csr_rw	otbn_csr_rw	6.000s	16.799us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	11.000s	543.929us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	17.949us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	10.000s	133.935us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	16.799us	1	1	100.00
		otbn_csr_aliasing	6.000s	17.949us	1	1	100.00
V1	mem_walk	otbn_mem_walk	21.000s	2.317ms	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	22.000s	1.561ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	21.000s	131.736us	1	1	100.00
V2	multi_error	otbn_multi_err	49.000s	353.623us	1	1	100.00
V2	back_to_back	otbn_multi	45.000s	416.924us	0	1	0.00
V2	stress_all	otbn_stress_all	40.000s	147.690us	1	1	100.00
V2	lc_escalation	otbn_escalate	8.000s	55.537us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	7.000s	16.349us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	11.000s	29.345us	1	1	100.00
V2	alert_test	otbn_alert_test	6.000s	18.662us	1	1	100.00
V2	intr_test	otbn_intr_test	8.000s	13.984us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	12.000s	534.795us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	12.000s	534.795us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	39.667us	1	1	100.00
		otbn_csr_rw	6.000s	16.799us	1	1	100.00
		otbn_csr_aliasing	6.000s	17.949us	1	1	100.00
		otbn_same_csr_outstanding	8.000s	31.235us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	39.667us	1	1	100.00
		otbn_csr_rw	6.000s	16.799us	1	1	100.00
		otbn_csr_aliasing	6.000s	17.949us	1	1	100.00
		otbn_same_csr_outstanding	8.000s	31.235us	1	1	100.00
V2		TOTAL			10	11	90.91
V2S	mem_integrity	otbn_imem_err	10.000s	47.681us	1	1	100.00
		otbn_dmem_err	12.000s	170.518us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	11.000s	211.413us	1	1	100.00
		otbn_controller_ispr_rdata_err	13.000s	31.163us	1	1	100.00
		otbn_mac_bignum_acc_err	9.000s	44.106us	1	1	100.00
		otbn_urnd_err	11.000s	39.907us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	31.307us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	177.073us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	8.000s	11.628us	0	1	0.00
V2S	tl_intg_err	otbn_sec_cm	1.733m	2.067ms	1	1	100.00
		otbn_tl_intg_err	36.000s	205.210us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	54.000s	401.583us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	1.733m	2.067ms	1	1	100.00
V2S	prim_count_check	otbn_sec_cm	1.733m	2.067ms	1	1	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	120.946us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	12.000s	170.518us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	10.000s	47.681us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	36.000s	205.210us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	8.000s	55.537us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	10.000s	47.681us	1	1	100.00
		otbn_dmem_err	12.000s	170.518us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	16.349us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	31.307us	1	1	100.00
		otbn_sec_cm	1.733m	2.067ms	1	1	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	1.733m	2.067ms	1	1	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	8.000s	19.510us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	10.000s	47.681us	1	1	100.00
		otbn_dmem_err	12.000s	170.518us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	16.349us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	31.307us	1	1	100.00
		otbn_sec_cm	1.733m	2.067ms	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	1.733m	2.067ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	8.000s	55.537us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	10.000s	47.681us	1	1	100.00
		otbn_dmem_err	12.000s	170.518us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	16.349us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	31.307us	1	1	100.00
		otbn_sec_cm	1.733m	2.067ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	1.733m	2.067ms	1	1	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	8.000s	19.510us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	12.000s	39.868us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	32.623us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	59.000s	1.014ms	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	59.000s	1.014ms	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	10.000s	88.473us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	1.733m	2.067ms	1	1	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	1.733m	2.067ms	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	12.000s	78.829us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	1.733m	2.067ms	1	1	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	1.733m	2.067ms	1	1	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	8.000s	16.219us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	8.000s	16.219us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	9.000s	46.289us	0	1	0.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	8.000s	19.510us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	8.000s	19.510us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	8.000s	19.510us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	45.000s	416.924us	0	1	0.00
V2S	sec_cm_ctrl_flow_count	otbn_single	8.000s	19.510us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	8.000s	19.510us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	10.000s	26.972us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	8.000s	19.510us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	1.733m	2.067ms	1	1	100.00
V2S		TOTAL			18	20	90.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	3.050m	3.593ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			38	41	92.68

Failure Buckets

• UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 1 failures:

  • Test otbn_multi has 1 failures.

    • 0.otbn_multi.54511036617443808429939052861033593498578697158858171192402792203258374325706
      Line 156, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_multi/latest/run.log

        UVM_FATAL @ 416923675 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
        UVM_INFO @ 416923675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:

  • Test otbn_sec_wipe_err has 1 failures.

    • 0.otbn_sec_wipe_err.113463781907287630513397406388295929507308458160320768457812734107992699322826
      Line 105, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 46288815 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
        UVM_ERROR @  46288815 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @  46288815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sim_*/tb.sv,292): Assertion MatchingStatus_A has failed has 1 failures:

  • Test otbn_partial_wipe has 1 failures.

    • 0.otbn_partial_wipe.6435068932706698942742040049598943554681015178214802360743340500121030915707
      Line 108, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_partial_wipe/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,292): (time 11627935 PS) Assertion tb.MatchingStatus_A has failed
        UVM_ERROR @  11627935 ps: (tb.sv:292) [ASSERT FAILED] MatchingStatus_A
        UVM_INFO @  11627935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---