PATTGEN Simulation Results

Wednesday April 09 2025 20:18:57 UTC

GitHub Revision: 96c9c77

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	6.000s	198.658us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	22.571us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	4.000s	37.634us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	7.000s	634.349us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	4.000s	29.559us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	39.576us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	4.000s	37.634us	1	1	100.00
		pattgen_csr_aliasing	4.000s	29.559us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	41.000s	2.804ms	1	1	100.00
V2	cnt_rollover	cnt_rollover	11.000s	1.793ms	1	1	100.00
V2	error	pattgen_error	4.000s	16.177us	1	1	100.00
V2	stress_all	pattgen_stress_all	21.000s	11.813ms	1	1	100.00
V2	alert_test	pattgen_alert_test	6.000s	13.145us	1	1	100.00
V2	intr_test	pattgen_intr_test	4.000s	91.280us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	358.388us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	358.388us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	22.571us	1	1	100.00
		pattgen_csr_rw	4.000s	37.634us	1	1	100.00
		pattgen_csr_aliasing	4.000s	29.559us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	24.813us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	22.571us	1	1	100.00
		pattgen_csr_rw	4.000s	37.634us	1	1	100.00
		pattgen_csr_aliasing	4.000s	29.559us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	24.813us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	5.000s	832.389us	1	1	100.00
		pattgen_sec_cm	4.000s	63.584us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	5.000s	832.389us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	2.083m	27.923ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	4.000s	120.357us	1	1	100.00
		TOTAL			17	18	94.44

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:908) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.54830493857668981520021134109348971155609120652339706629152543750622560391150
      Line 239, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9187286569 ps: (cip_base_vseq.sv:908) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 9187321901 ps: (cip_base_vseq.sv:812) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 9187321901 ps: (cip_base_vseq.sv:815) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 3/10
        UVM_INFO @ 9187405235 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]