ROM_CTRL/32KB Simulation Results

Wednesday April 09 2025 20:18:57 UTC

GitHub Revision: 96c9c77

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 4.940s 166.421us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 6.710s 133.797us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 4.550s 219.994us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 5.390s 127.270us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.340s 130.076us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 5.280s 174.429us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 4.550s 219.994us 1 1 100.00
rom_ctrl_csr_aliasing 4.340s 130.076us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 3.940s 292.048us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 3.690s 403.603us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 7.270s 131.391us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 16.900s 611.234us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 8.800s 303.873us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 6.540s 170.398us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 7.060s 557.170us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 7.060s 557.170us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 6.710s 133.797us 1 1 100.00
rom_ctrl_csr_rw 4.550s 219.994us 1 1 100.00
rom_ctrl_csr_aliasing 4.340s 130.076us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.530s 299.653us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 6.710s 133.797us 1 1 100.00
rom_ctrl_csr_rw 4.550s 219.994us 1 1 100.00
rom_ctrl_csr_aliasing 4.340s 130.076us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.530s 299.653us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 2.614m 15.184ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 26.220s 3.291ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 1.547m 455.537us 1 1 100.00
rom_ctrl_tl_intg_err 23.850s 305.749us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.547m 455.537us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 1.547m 455.537us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.614m 15.184ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.614m 15.184ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.614m 15.184ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.614m 15.184ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.614m 15.184ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.547m 455.537us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.547m 455.537us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 4.940s 166.421us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 4.940s 166.421us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 4.940s 166.421us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 23.850s 305.749us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.614m 15.184ms 1 1 100.00
rom_ctrl_kmac_err_chk 8.800s 303.873us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 2.614m 15.184ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 2.614m 15.184ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 2.614m 15.184ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 26.220s 3.291ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.547m 455.537us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 58.170s 1.358ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00