ROM_CTRL/64KB Simulation Results

Wednesday April 09 2025 20:18:57 UTC

GitHub Revision: 96c9c77

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 11.150s 2.052ms 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 8.280s 305.738us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 6.970s 292.726us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.900s 534.983us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 9.410s 1.203ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.120s 681.129us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 6.970s 292.726us 1 1 100.00
rom_ctrl_csr_aliasing 9.410s 1.203ms 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 8.650s 10.996ms 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 5.490s 378.819us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 7.870s 1.103ms 1 1 100.00
V2 stress_all rom_ctrl_stress_all 20.750s 3.226ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 13.050s 1.816ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 7.400s 296.561us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 9.160s 1.063ms 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 9.160s 1.063ms 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 8.280s 305.738us 1 1 100.00
rom_ctrl_csr_rw 6.970s 292.726us 1 1 100.00
rom_ctrl_csr_aliasing 9.410s 1.203ms 1 1 100.00
rom_ctrl_same_csr_outstanding 5.740s 359.920us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 8.280s 305.738us 1 1 100.00
rom_ctrl_csr_rw 6.970s 292.726us 1 1 100.00
rom_ctrl_csr_aliasing 9.410s 1.203ms 1 1 100.00
rom_ctrl_same_csr_outstanding 5.740s 359.920us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.486m 2.295ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 34.980s 1.561ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 5.242m 1.954ms 1 1 100.00
rom_ctrl_tl_intg_err 1.093m 888.612us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 5.242m 1.954ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 5.242m 1.954ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.486m 2.295ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.486m 2.295ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.486m 2.295ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.486m 2.295ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.486m 2.295ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 5.242m 1.954ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 5.242m 1.954ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 11.150s 2.052ms 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 11.150s 2.052ms 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 11.150s 2.052ms 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.093m 888.612us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.486m 2.295ms 1 1 100.00
rom_ctrl_kmac_err_chk 13.050s 1.816ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.486m 2.295ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.486m 2.295ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.486m 2.295ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 34.980s 1.561ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 5.242m 1.954ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 46.870s 1.304ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00