RV_DM/USE_JTAG_INTERFACE Simulation Results

Wednesday April 09 2025 20:18:57 UTC

GitHub Revision: 96c9c77

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 9.090s 3.200ms 1 1 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 2.950s 160.276us 1 1 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 2.380s 491.198us 1 1 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 9.380s 3.941ms 1 1 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 2.660s 608.619us 1 1 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 5.900s 3.549ms 1 1 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 1.870s 1.598ms 1 1 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 16.400s 24.904ms 1 1 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 37.640s 48.196ms 1 1 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 3.020s 519.492us 1 1 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 2.210s 888.634us 1 1 100.00
V1 cmderr_exception rv_dm_cmderr_exception 2.070s 277.613us 1 1 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 1.990s 305.357us 1 1 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.720s 79.200us 1 1 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 2.100s 506.161us 1 1 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.820s 67.124us 1 1 100.00
V1 halt_resume rv_dm_halt_resume_whereto 2.360s 177.862us 1 1 100.00
V1 progbuf_busy rv_dm_cmderr_busy 3.020s 519.492us 1 1 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 2.170s 443.530us 1 1 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 2.200s 241.118us 1 1 100.00
V1 progbuf_exception rv_dm_cmderr_exception 2.070s 277.613us 1 1 100.00
V1 rom_read_access rv_dm_rom_read_access 1.810s 44.864us 1 1 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.300s 153.953us 1 1 100.00
V1 csr_rw rv_dm_csr_rw 2.180s 139.560us 1 1 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 23.900s 3.089ms 1 1 100.00
V1 csr_aliasing rv_dm_csr_aliasing 21.860s 1.745ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 1.780s 50.598us 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 21.860s 1.745ms 1 1 100.00
rv_dm_csr_rw 2.180s 139.560us 1 1 100.00
V1 mem_walk rv_dm_mem_walk 1.570s 38.359us 1 1 100.00
V1 mem_partial_access rv_dm_mem_partial_access 1.670s 174.720us 1 1 100.00
V1 TOTAL 26 27 96.30
V2 idcode rv_dm_smoke 9.090s 3.200ms 1 1 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 2.140s 548.223us 1 1 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.970s 138.242us 1 1 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 2.370s 333.218us 1 1 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 3.210s 1.920ms 1 1 100.00
V2 sba rv_dm_sba_tl_access 7.170s 3.789ms 1 1 100.00
rv_dm_delayed_resp_sba_tl_access 2.370s 624.545us 0 1 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 8.590s 11.912ms 1 1 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 6.740s 3.744ms 1 1 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 2.440s 332.053us 1 1 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 2.840s 1.005ms 1 1 100.00
V2 ndmreset_req rv_dm_ndmreset_req 1.870s 253.358us 1 1 100.00
V2 hart_unavail rv_dm_hart_unavail 2.020s 363.064us 1 1 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 18.000s 8.586ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 1.630s 23.107us 0 1 0.00
V2 hartsel_warl rv_dm_hartsel_warl 1.680s 88.363us 1 1 100.00
V2 stress_all rv_dm_stress_all 5.790s 6.095ms 1 1 100.00
V2 alert_test rv_dm_alert_test 1.750s 92.316us 1 1 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 1.620s 43.030us 0 1 0.00
V2 tl_d_illegal_access rv_dm_tl_errors 1.620s 43.030us 0 1 0.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 21.860s 1.745ms 1 1 100.00
rv_dm_csr_hw_reset 2.300s 153.953us 1 1 100.00
rv_dm_csr_rw 2.180s 139.560us 1 1 100.00
rv_dm_same_csr_outstanding 6.100s 167.977us 1 1 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 21.860s 1.745ms 1 1 100.00
rv_dm_csr_hw_reset 2.300s 153.953us 1 1 100.00
rv_dm_csr_rw 2.180s 139.560us 1 1 100.00
rv_dm_same_csr_outstanding 6.100s 167.977us 1 1 100.00
V2 TOTAL 16 19 84.21
V2S tl_intg_err rv_dm_sec_cm 2.470s 456.544us 1 1 100.00
rv_dm_tl_intg_err 13.950s 4.674ms 1 1 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 13.950s 4.674ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 2.840s 1.005ms 1 1 100.00
rv_dm_debug_disabled 1.760s 51.684us 1 1 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 2.840s 1.005ms 1 1 100.00
rv_dm_debug_disabled 1.760s 51.684us 1 1 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 9.090s 3.200ms 1 1 100.00
V2S sec_cm_dm_en_ctrl_lc_gated rv_dm_buffered_enable 2.040s 316.533us 1 1 100.00
V2S sec_cm_sba_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 2.160s 261.523us 1 1 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 2.160s 261.523us 1 1 100.00
V2S sec_cm_exec_ctrl_mubi rv_dm_buffered_enable 2.040s 316.533us 1 1 100.00
V2S TOTAL 5 5 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 1.920s 88.587us 0 1 0.00
V3 TOTAL 0 1 0.00
Unmapped tests rv_dm_scanmode 1.660s 13.067us 1 1 100.00
TOTAL 48 53 90.57

Failure Buckets