RV_TIMER Simulation Results

Wednesday April 09 2025 20:18:57 UTC

GitHub Revision: 96c9c77

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	3.328m	358.526ms	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.810s	12.549us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.840s	13.259us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.350s	1.026ms	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.550s	334.170us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.770s	103.742us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.840s	13.259us	1	1	100.00
		rv_timer_csr_aliasing	1.550s	334.170us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	13.328m	375.320ms	1	1	100.00
V2	disabled	rv_timer_disabled	1.490m	150.491ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	1.693m	164.168ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	1.693m	164.168ms	1	1	100.00
V2	stress	rv_timer_stress_all	7.480m	281.118ms	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.760s	53.065us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.160s	160.140us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.160s	160.140us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.810s	12.549us	1	1	100.00
		rv_timer_csr_rw	1.840s	13.259us	1	1	100.00
		rv_timer_csr_aliasing	1.550s	334.170us	1	1	100.00
		rv_timer_same_csr_outstanding	1.430s	21.803us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.810s	12.549us	1	1	100.00
		rv_timer_csr_rw	1.840s	13.259us	1	1	100.00
		rv_timer_csr_aliasing	1.550s	334.170us	1	1	100.00
		rv_timer_same_csr_outstanding	1.430s	21.803us	1	1	100.00
V2		TOTAL			7	7	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.800s	63.963us	1	1	100.00
		rv_timer_tl_intg_err	2.380s	128.979us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.380s	128.979us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	19.900s	10.047ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			16	16	100.00