SPI_DEVICE/1R1W Simulation Results

Wednesday April 09 2025 20:18:57 UTC

GitHub Revision: 96c9c77

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.744m	34.103ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.650s	31.701us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.640s	37.733us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	23.160s	2.349ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	6.170s	1.615ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.370s	151.899us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.640s	37.733us	1	1	100.00
		spi_device_csr_aliasing	6.170s	1.615ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.480s	11.402us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.010s	113.574us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.690s	175.777us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.770s	5.065us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.640s	1.758us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	3.980s	392.763us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	3.980s	392.763us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	1.970s	113.951us	1	1	100.00
		spi_device_tpm_sts_read	1.770s	20.177us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	12.750s	1.080ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	4.240s	1.831ms	1	1	100.00
		spi_device_flash_all	1.520m	21.822ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	5.410s	386.616us	1	1	100.00
		spi_device_flash_all	1.520m	21.822ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	5.410s	386.616us	1	1	100.00
		spi_device_flash_all	1.520m	21.822ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.520m	21.822ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	5.260s	356.810us	1	1	100.00
		spi_device_flash_all	1.520m	21.822ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	5.260s	356.810us	1	1	100.00
		spi_device_flash_all	1.520m	21.822ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	5.260s	356.810us	1	1	100.00
		spi_device_flash_all	1.520m	21.822ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	5.260s	356.810us	1	1	100.00
		spi_device_flash_all	1.520m	21.822ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	5.260s	356.810us	1	1	100.00
		spi_device_flash_all	1.520m	21.822ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	4.070s	137.110us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	9.750s	984.046us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	9.750s	984.046us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	9.750s	984.046us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	7.520s	207.390us	1	1	100.00
		spi_device_read_buffer_direct	9.760s	5.141ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	9.750s	984.046us	1	1	100.00
		spi_device_flash_all	1.520m	21.822ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.520m	21.822ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.520m	21.822ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.550s	358.140us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.550s	358.140us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.744m	34.103ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	2.718m	80.917ms	1	1	100.00
V2	stress_all	spi_device_stress_all	21.940s	7.056ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.730s	60.374us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.510s	43.990us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.230s	106.006us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.230s	106.006us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.650s	31.701us	1	1	100.00
		spi_device_csr_rw	1.640s	37.733us	1	1	100.00
		spi_device_csr_aliasing	6.170s	1.615ms	1	1	100.00
		spi_device_same_csr_outstanding	2.910s	110.966us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.650s	31.701us	1	1	100.00
		spi_device_csr_rw	1.640s	37.733us	1	1	100.00
		spi_device_csr_aliasing	6.170s	1.615ms	1	1	100.00
		spi_device_same_csr_outstanding	2.910s	110.966us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.890s	318.159us	1	1	100.00
		spi_device_tl_intg_err	11.040s	601.620us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	11.040s	601.620us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	22.070s	6.772ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.34244052443159938386987890619423457095233434087752551422988863416111161627722
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   4344894 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[105])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   4344894 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   4344894 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[1001])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.2096322359647292128145152041625784118222289444416270825753914952861979112805
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1135692 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1135692 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   1207692 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa73ba [10100111001110111010] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   1207692 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0xa73ba [10100111001110111010] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])