SPI_DEVICE/2P Simulation Results

Wednesday April 09 2025 20:18:57 UTC

GitHub Revision: 96c9c77

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	22.310s	5.757ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.020s	295.995us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.710s	62.082us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	24.780s	1.880ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.970s	947.521us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.240s	111.294us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.710s	62.082us	1	1	100.00
		spi_device_csr_aliasing	16.970s	947.521us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.650s	18.223us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.930s	21.384us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.780s	15.791us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.790s	17.363us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	1.660s	2.533us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.670s	15.179us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.670s	15.179us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	10.420s	16.373ms	1	1	100.00
		spi_device_tpm_sts_read	1.750s	204.753us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	18.380s	38.266ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	6.080s	1.231ms	1	1	100.00
		spi_device_flash_all	1.482m	73.419ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	9.840s	3.595ms	1	1	100.00
		spi_device_flash_all	1.482m	73.419ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	9.840s	3.595ms	1	1	100.00
		spi_device_flash_all	1.482m	73.419ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.482m	73.419ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	12.320s	1.885ms	1	1	100.00
		spi_device_flash_all	1.482m	73.419ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	12.320s	1.885ms	1	1	100.00
		spi_device_flash_all	1.482m	73.419ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	12.320s	1.885ms	1	1	100.00
		spi_device_flash_all	1.482m	73.419ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	12.320s	1.885ms	1	1	100.00
		spi_device_flash_all	1.482m	73.419ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	12.320s	1.885ms	1	1	100.00
		spi_device_flash_all	1.482m	73.419ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	7.250s	7.432ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	4.880s	391.037us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	4.880s	391.037us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	4.880s	391.037us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	3.110s	224.592us	1	1	100.00
		spi_device_read_buffer_direct	4.770s	776.938us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	4.880s	391.037us	1	1	100.00
		spi_device_flash_all	1.482m	73.419ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.482m	73.419ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.482m	73.419ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.220s	976.778us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.220s	976.778us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	22.310s	5.757ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	50.310s	45.601ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.670s	441.340us	1	1	100.00
V2	alert_test	spi_device_alert_test	1.410s	52.170us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.580s	15.764us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.930s	634.759us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.930s	634.759us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.020s	295.995us	1	1	100.00
		spi_device_csr_rw	2.710s	62.082us	1	1	100.00
		spi_device_csr_aliasing	16.970s	947.521us	1	1	100.00
		spi_device_same_csr_outstanding	4.330s	209.761us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.020s	295.995us	1	1	100.00
		spi_device_csr_rw	2.710s	62.082us	1	1	100.00
		spi_device_csr_aliasing	16.970s	947.521us	1	1	100.00
		spi_device_same_csr_outstanding	4.330s	209.761us	1	1	100.00
V2		TOTAL			21	22	95.45
V2S	tl_intg_err	spi_device_sec_cm	1.910s	1.215ms	1	1	100.00
		spi_device_tl_intg_err	7.300s	743.033us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	7.300s	743.033us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	3.071m	152.698ms	1	1	100.00
		TOTAL			32	33	96.97

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:
  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.87063349933740859139460793200105425935988558047640388130290142993699032653053
      Line 71, in log /nightly/runs/scratch/master/spi_device_2p-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1708412 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1708412 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   1746412 ps: (spi_device_ram_cfg_vseq.sv:23) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === dst_ram_cfg (0xdd2d18 [110111010010110100011000] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   1746412 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)