SPI_HOST Simulation Results

Wednesday April 09 2025 20:18:57 UTC

GitHub Revision: 96c9c77

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	13.000s	2.217ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	12.000s	16.319us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	12.000s	40.432us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	12.000s	69.957us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	10.000s	167.829us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	7.000s	91.697us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	12.000s	40.432us	1	1	100.00
		spi_host_csr_aliasing	10.000s	167.829us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	14.000s	24.388us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	12.000s	43.111us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	4.000s	304.595us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	5.000s	152.985us	1	1	100.00
		spi_host_error_cmd	4.000s	19.900us	1	1	100.00
		spi_host_event	6.000s	1.071ms	1	1	100.00
V2	clock_rate	spi_host_speed	6.000s	193.407us	1	1	100.00
V2	speed	spi_host_speed	6.000s	193.407us	1	1	100.00
V2	chip_select_timing	spi_host_speed	6.000s	193.407us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	7.000s	144.000us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	253.242us	1	1	100.00
V2	cpol_cpha	spi_host_speed	6.000s	193.407us	1	1	100.00
V2	full_cycle	spi_host_speed	6.000s	193.407us	1	1	100.00
V2	duplex	spi_host_smoke	13.000s	2.217ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	13.000s	2.217ms	1	1	100.00
V2	stress_all	spi_host_stress_all	5.000s	74.611us	1	1	100.00
V2	spien	spi_host_spien	9.000s	1.073ms	1	1	100.00
V2	stall	spi_host_status_stall	27.000s	743.252us	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	4.000s	98.292us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	5.000s	152.985us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	18.927us	1	1	100.00
V2	intr_test	spi_host_intr_test	14.000s	17.480us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	17.000s	417.908us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	17.000s	417.908us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	12.000s	16.319us	1	1	100.00
		spi_host_csr_rw	12.000s	40.432us	1	1	100.00
		spi_host_csr_aliasing	10.000s	167.829us	1	1	100.00
		spi_host_same_csr_outstanding	9.000s	37.828us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	12.000s	16.319us	1	1	100.00
		spi_host_csr_rw	12.000s	40.432us	1	1	100.00
		spi_host_csr_aliasing	10.000s	167.829us	1	1	100.00
		spi_host_same_csr_outstanding	9.000s	37.828us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	14.000s	71.566us	1	1	100.00
		spi_host_sec_cm	4.000s	78.941us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	14.000s	71.566us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	52.533m	100.002ms	0	1	0.00
		TOTAL			25	26	96.15

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 0.spi_host_upper_range_clkdiv.52199276772088067102568731733849473854700018724812335996434916354694463126194
      Line 164, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100002453792 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x8b004f14, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
        UVM_INFO @ 100002453792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---