SRAM_CTRL/MAIN Simulation Results

Wednesday April 09 2025 20:18:57 UTC

GitHub Revision: 96c9c77

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	8.030s	3.087ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.760s	23.207us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.540s	13.985us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.970s	26.452us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.780s	17.753us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.460s	350.515us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.540s	13.985us	1	1	100.00
		sram_ctrl_csr_aliasing	1.780s	17.753us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	2.042m	41.348ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.748m	4.367ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	4.230m	10.756ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.683m	8.137ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	14.594m	193.071ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	3.760m	7.196ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	16.950s	25.965ms	1	1	100.00
V2	executable	sram_ctrl_executable	4.140m	8.052ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	20.570s	8.512ms	1	1	100.00
		sram_ctrl_partial_access_b2b	4.233m	6.190ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	9.990s	2.796ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	14.330s	1.414ms	1	1	100.00
		sram_ctrl_throughput_w_readback	33.870s	1.677ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	4.840m	48.379ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	6.390s	4.789ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	31.541m	442.786ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.630s	34.359us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.380s	130.562us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.380s	130.562us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.760s	23.207us	1	1	100.00
		sram_ctrl_csr_rw	1.540s	13.985us	1	1	100.00
		sram_ctrl_csr_aliasing	1.780s	17.753us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.560s	15.813us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.760s	23.207us	1	1	100.00
		sram_ctrl_csr_rw	1.540s	13.985us	1	1	100.00
		sram_ctrl_csr_aliasing	1.780s	17.753us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.560s	15.813us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	18.980s	10.608ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.970s	42.889us	0	1	0.00
		sram_ctrl_tl_intg_err	2.780s	397.976us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.970s	42.889us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.780s	397.976us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	4.840m	48.379ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	4.840m	48.379ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.540s	13.985us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	4.140m	8.052ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	4.140m	8.052ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	4.140m	8.052ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	16.950s	25.965ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	5.340s	2.798ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	18.980s	10.608ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	6.620s	2.758ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	8.030s	3.087ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	8.030s	3.087ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	4.140m	8.052ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.970s	42.889us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	16.950s	25.965ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.970s	42.889us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.970s	42.889us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	8.030s	3.087ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.970s	42.889us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	17.860s	2.941ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.45039328179214754015938721120293815435682481197270547015302915581996913847123
      Line 101, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  42888827 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  42888827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---