SRAM_CTRL/RET Simulation Results

Wednesday April 09 2025 20:18:57 UTC

GitHub Revision: 96c9c77

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	9.440s	687.079us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.560s	42.701us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.460s	20.023us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.280s	160.805us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.700s	63.368us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.720s	224.745us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.460s	20.023us	1	1	100.00
		sram_ctrl_csr_aliasing	1.700s	63.368us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.790s	671.351us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	4.170s	121.681us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	13.943m	15.773ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.560m	7.861ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	50.290s	16.222ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	1.964m	1.545ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	3.200s	422.503us	1	1	100.00
V2	executable	sram_ctrl_executable	3.673m	2.457ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	12.460s	583.248us	1	1	100.00
		sram_ctrl_partial_access_b2b	6.412m	21.131ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.840s	41.244us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	49.780s	637.634us	1	1	100.00
		sram_ctrl_throughput_w_readback	16.600s	172.101us	1	1	100.00
V2	regwen	sram_ctrl_regwen	6.786m	13.973ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.720s	58.002us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	5.674m	10.067ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.700s	43.157us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.500s	193.010us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.500s	193.010us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.560s	42.701us	1	1	100.00
		sram_ctrl_csr_rw	1.460s	20.023us	1	1	100.00
		sram_ctrl_csr_aliasing	1.700s	63.368us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.730s	23.883us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.560s	42.701us	1	1	100.00
		sram_ctrl_csr_rw	1.460s	20.023us	1	1	100.00
		sram_ctrl_csr_aliasing	1.700s	63.368us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.730s	23.883us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.840s	773.322us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.750s	3.968us	0	1	0.00
		sram_ctrl_tl_intg_err	2.240s	115.271us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.750s	3.968us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.240s	115.271us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	6.786m	13.973ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	6.786m	13.973ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.460s	20.023us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	3.673m	2.457ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	3.673m	2.457ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	3.673m	2.457ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	3.200s	422.503us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.940s	78.392us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.840s	773.322us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.050s	33.108us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	9.440s	687.079us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	9.440s	687.079us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	3.673m	2.457ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.750s	3.968us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	3.200s	422.503us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.750s	3.968us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.750s	3.968us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	9.440s	687.079us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.750s	3.968us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	57.430s	1.423ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(depth_o <= *'(Depth))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.1799606500452822984900250008839921293591071287843058440786436467768833394530
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   3968027 ps: (prim_fifo_sync.sv:209) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   3968027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---