SYSRST_CTRL Simulation Results

Wednesday April 09 2025 20:18:57 UTC

GitHub Revision: 96c9c77

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 5.470s 2.111ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 4.860s 2.470ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 3.720s 2.462ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 2.990s 2.564ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 5.550s 6.060ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 3.320s 2.067ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 16.370s 35.925ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 7.830s 3.213ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 2.790s 2.164ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 3.320s 2.067ms 1 1 100.00
sysrst_ctrl_csr_aliasing 7.830s 3.213ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 3.205m 100.735ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 46.530s 24.831ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 5.570s 3.343ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 6.620s 4.095ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 3.850s 2.516ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 3.610s 2.139ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 8.680s 3.891ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 1.830s 2.705ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 1.334m 2.210s 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 17.650s 36.101ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 12.350s 14.486ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 2.360s 2.039ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 7.340s 2.014ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 3.260s 2.373ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 3.260s 2.373ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 5.550s 6.060ms 1 1 100.00
sysrst_ctrl_csr_rw 3.320s 2.067ms 1 1 100.00
sysrst_ctrl_csr_aliasing 7.830s 3.213ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 4.460s 4.552ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 5.550s 6.060ms 1 1 100.00
sysrst_ctrl_csr_rw 3.320s 2.067ms 1 1 100.00
sysrst_ctrl_csr_aliasing 7.830s 3.213ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 4.460s 4.552ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 43.530s 22.014ms 1 1 100.00
sysrst_ctrl_tl_intg_err 44.150s 42.535ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 44.150s 42.535ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 5.850s 26.343ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00