UART Simulation Results

Wednesday April 09 2025 20:18:57 UTC

GitHub Revision: 96c9c77

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.630s	931.508us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.450s	20.636us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.600s	27.457us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.940s	258.621us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.770s	105.505us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.550s	25.089us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.600s	27.457us	1	1	100.00
		uart_csr_aliasing	1.770s	105.505us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	12.820s	22.428ms	1	1	100.00
V2	parity	uart_smoke	2.630s	931.508us	1	1	100.00
		uart_tx_rx	12.820s	22.428ms	1	1	100.00
V2	parity_error	uart_intr	7.100s	16.277ms	1	1	100.00
		uart_rx_parity_err	2.083m	218.904ms	1	1	100.00
V2	watermark	uart_tx_rx	12.820s	22.428ms	1	1	100.00
		uart_intr	7.100s	16.277ms	1	1	100.00
V2	fifo_full	uart_fifo_full	1.986m	224.992ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	13.850s	47.684ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	35.340s	51.456ms	1	1	100.00
V2	rx_frame_err	uart_intr	7.100s	16.277ms	1	1	100.00
V2	rx_break_err	uart_intr	7.100s	16.277ms	1	1	100.00
V2	rx_timeout	uart_intr	7.100s	16.277ms	1	1	100.00
V2	perf	uart_perf	3.493m	20.438ms	1	1	100.00
V2	sys_loopback	uart_loopback	5.010s	5.329ms	1	1	100.00
V2	line_loopback	uart_loopback	5.010s	5.329ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	1.666m	75.698ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	3.920s	2.073ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.790s	914.621us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	3.910s	1.864ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	2.921m	203.480ms	1	1	100.00
V2	stress_all	uart_stress_all	1.671m	112.698ms	1	1	100.00
V2	alert_test	uart_alert_test	1.550s	52.558us	1	1	100.00
V2	intr_test	uart_intr_test	1.460s	93.641us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.460s	191.337us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.460s	191.337us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.450s	20.636us	1	1	100.00
		uart_csr_rw	1.600s	27.457us	1	1	100.00
		uart_csr_aliasing	1.770s	105.505us	1	1	100.00
		uart_same_csr_outstanding	1.700s	77.615us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.450s	20.636us	1	1	100.00
		uart_csr_rw	1.600s	27.457us	1	1	100.00
		uart_csr_aliasing	1.770s	105.505us	1	1	100.00
		uart_same_csr_outstanding	1.700s	77.615us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.890s	308.824us	1	1	100.00
		uart_tl_intg_err	1.970s	775.167us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.970s	775.167us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	51.730s	4.545ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00