CHIP Simulation Results

Wednesday April 09 2025 20:18:57 UTC

GitHub Revision: `96c9c77`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.867m	2.631ms	1	1	100.00
		chip_sw_example_rom	1.337m	2.572ms	1	1	100.00
		chip_sw_example_manufacturer	2.234m	2.682ms	1	1	100.00
		chip_sw_example_concurrency	2.621m	3.048ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	2.355m	4.275ms	1	1	100.00
V1	csr_rw	chip_csr_rw	6.553m	5.908ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	13.276m	10.642ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.024h	32.668ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	54.470s	1.842ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.024h	32.668ms	1	1	100.00
		chip_csr_rw	6.553m	5.908ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	5.870s	175.054us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.317m	4.172ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.317m	4.172ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.317m	4.172ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.518m	4.503ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.518m	4.503ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.433m	4.094ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	6.065m	4.242ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	6.106m	3.830ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	28.912m	13.758ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	15.740m	8.192ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	11.309m	8.229ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.484m	4.531ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.484m	4.531ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.855m	3.822ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	4.677m	6.331ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.878m	3.093ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	14.013m	14.198ms	1	1	100.00
		chip_tap_straps_testunlock0	3.198m	4.268ms	1	1	100.00
		chip_tap_straps_rma	2.000m	2.483ms	1	1	100.00
		chip_tap_straps_prod	9.067m	9.889ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.177m	2.744ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	10.813m	7.884ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	7.737m	6.120ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	7.737m	6.120ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	7.591m	7.175ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	31.842m	18.957ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.109m	3.264ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.649m	5.168ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.139m	19.071ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.692m	2.525ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	7.865m	5.438ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.254m	2.728ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	14.526m	9.947ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.717m	2.743ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.584m	4.305ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.430m	2.676ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.434m	3.442ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	7.300m	8.334ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.550m	4.545ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.127m	3.364ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.550m	4.545ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.016m	2.767ms	1	1	100.00
		chip_sw_aes_smoketest	2.188m	2.369ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.222m	3.531ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.097m	3.069ms	1	1	100.00
		chip_sw_csrng_smoketest	2.613m	3.209ms	1	1	100.00
		chip_sw_entropy_src_smoketest	5.280m	3.497ms	1	1	100.00
		chip_sw_gpio_smoketest	3.409m	3.173ms	1	1	100.00
		chip_sw_hmac_smoketest	3.160m	3.626ms	1	1	100.00
		chip_sw_kmac_smoketest	2.893m	3.235ms	1	1	100.00
		chip_sw_otbn_smoketest	12.897m	8.577ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.741m	6.805ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.974m	5.544ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.583m	3.521ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.491m	2.284ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.978m	2.951ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.106m	2.869ms	1	1	100.00
		chip_sw_uart_smoketest	2.365m	3.152ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	1.743m	2.726ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.208m	4.631ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.916h	60.900ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	37.857m	14.686ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.165m	4.667ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.728m	2.979ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.519m	3.083ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.743h	52.757ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.879h	57.579ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	1.009m	2.645ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	1.009m	2.645ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.024h	32.668ms	1	1	100.00
		chip_same_csr_outstanding	39.519m	28.844ms	1	1	100.00
		chip_csr_hw_reset	2.355m	4.275ms	1	1	100.00
		chip_csr_rw	6.553m	5.908ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.024h	32.668ms	1	1	100.00
		chip_same_csr_outstanding	39.519m	28.844ms	1	1	100.00
		chip_csr_hw_reset	2.355m	4.275ms	1	1	100.00
		chip_csr_rw	6.553m	5.908ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	16.940s	802.957us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	5.040s	47.171us	1	1	100.00
		xbar_smoke_large_delays	32.910s	5.378ms	1	1	100.00
		xbar_smoke_slow_rsp	35.510s	3.766ms	1	1	100.00
		xbar_random_zero_delays	5.310s	40.196us	1	1	100.00
		xbar_random_large_delays	3.786m	38.465ms	1	1	100.00
		xbar_random_slow_rsp	30.630s	3.376ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	12.140s	168.849us	1	1	100.00
		xbar_error_and_unmapped_addr	7.700s	89.444us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	12.350s	577.129us	1	1	100.00
		xbar_error_and_unmapped_addr	7.700s	89.444us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.188m	3.296ms	1	1	100.00
		xbar_access_same_device_slow_rsp	7.411m	53.144ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	12.430s	373.031us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.517m	4.407ms	1	1	100.00
		xbar_stress_all_with_error	2.407m	8.124ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	1.334m	307.886us	1	1	100.00
		xbar_stress_all_with_reset_error	1.282m	475.075us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	37.857m	14.686ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	32.990m	28.285ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	39.701m	15.213ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	31.091m	11.076ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	39.472m	15.250ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	40.397m	16.287ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	41.201m	15.732ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	38.552m	14.568ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	28.050s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	28.450s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	29.750s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	28.380s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	27.000s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	26.650s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	27.160s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	26.660s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	26.060s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	25.760s	10.360us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	26.030s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	26.210s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	25.800s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	25.800s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	25.060s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	26.140s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	26.190s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	26.150s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	25.600s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	26.010s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	26.060s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	26.380s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	26.000s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	25.310s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	26.740s	10.240us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	29.619m	11.388ms	1	1	100.00
		rom_e2e_asm_init_dev	36.682m	15.442ms	1	1	100.00
		rom_e2e_asm_init_prod	37.731m	14.963ms	1	1	100.00
		rom_e2e_asm_init_prod_end	36.441m	15.821ms	1	1	100.00
		rom_e2e_asm_init_rma	35.242m	15.165ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	36.346m	15.516ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	35.253m	14.392ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	35.592m	15.689ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	37.295m	16.149ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	7.281m	18.262ms	1	1	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	7.281m	18.262ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.769m	3.384ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.692m	2.525ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.497m	2.592ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.356m	2.328ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	22.257m	11.141ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.498m	2.258ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.373m	4.193ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	5.206m	4.411ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.543m	5.222ms	1	1	100.00
		chip_plic_all_irqs_10	5.347m	3.441ms	1	1	100.00
		chip_plic_all_irqs_20	5.885m	4.560ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.833m	3.713ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	19.365m	12.857ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.547m	3.569ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.594m	2.809ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	8.003m	10.491ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	22.459m	9.439ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	13.782m	7.596ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	12.441m	7.508ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.312h	255.139ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.091m	3.114ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.741m	6.805ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.091m	3.114ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	9.989m	8.769ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	9.989m	8.769ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.582m	6.594ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	4.350m	5.746ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	10.083m	6.312ms	1	1	100.00
		chip_sw_aes_idle	2.356m	2.328ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.596m	3.203ms	1	1	100.00
		chip_sw_kmac_idle	2.185m	2.973ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.289m	3.422ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	4.344m	3.305ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.301m	3.990ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	3.826m	4.832ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	10.710m	9.148ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.618m	3.843ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.799m	4.682ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.963m	3.928ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.847m	4.610ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.935m	4.481ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.185m	4.653ms	1	1	100.00
		chip_sw_ast_clk_outputs	7.591m	7.175ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	9.173m	12.028ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.963m	3.928ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.847m	4.610ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.109m	3.264ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.649m	5.168ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.139m	19.071ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.692m	2.525ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	7.865m	5.438ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.254m	2.728ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	14.526m	9.947ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.717m	2.743ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.584m	4.305ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.430m	2.676ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.107m	3.040ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.621m	4.730ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.220m	6.620ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	49.139m	24.486ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.273m	3.732ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.754m	3.182ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	17.359m	11.444ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.589m	3.444ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.850m	5.680ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	18.868m	18.592ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	2.886h	136.839ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	7.591m	7.175ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.408m	4.710ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	4.196m	3.468ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	5.206m	4.411ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	22.459m	9.439ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	14.708m	6.461ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.987m	2.991ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.116m	6.699ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	1.985m	2.510ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	30.480m	12.825ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.587m	2.475ms	1	1	100.00
		chip_sw_edn_entropy_reqs	11.212m	6.094ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.587m	2.475ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	14.708m	6.461ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.708m	2.909ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	18.591m	22.479ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	8.304m	5.542ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.649m	5.168ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.327m	4.097ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.109m	3.264ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	50.636m	44.277ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	18.591m	22.479ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.582m	3.245ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	20.418m	10.026ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.365m	4.717ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	50.636m	44.277ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.365m	4.717ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.365m	4.717ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	5.365m	4.717ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.365m	4.717ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	5.206m	4.411ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	1.815m	4.847ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.662m	4.940ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.730m	5.461ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.730m	5.461ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.300m	2.776ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.254m	2.728ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.596m	3.203ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	3.359m	3.859ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	15.671m	7.164ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	8.069m	5.482ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	6.520m	4.674ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	5.353m	4.970ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.194m	3.658ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	20.418m	10.026ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	14.526m	9.947ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	21.156m	10.248ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	22.257m	11.141ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	44.760m	14.301ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.384m	3.362ms	1	1	100.00
		chip_sw_kmac_mode_kmac	3.027m	2.452ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.717m	2.743ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	20.418m	10.026ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	7.792m	13.143ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	1.988m	2.878ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	24.361m	11.158ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.185m	2.973ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.373m	4.193ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	14.013m	14.198ms	1	1	100.00
		chip_tap_straps_rma	2.000m	2.483ms	1	1	100.00
		chip_tap_straps_prod	9.067m	9.889ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	3.089m	3.097ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	7.792m	13.143ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	7.792m	13.143ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	7.792m	13.143ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	8.837m	7.110ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	5.365m	4.717ms	1	1	100.00
		chip_sw_flash_rma_unlocked	50.636m	44.277ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.020m	3.005ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.295m	6.099ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	10.558m	7.994ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.139m	6.105ms	1	1	100.00
		chip_sw_lc_ctrl_transition	7.792m	13.143ms	1	1	100.00
		chip_sw_keymgr_key_derivation	20.418m	10.026ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	4.742m	9.617ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	7.683m	6.202ms	1	1	100.00
		chip_prim_tl_access	1.815m	4.847ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	9.173m	12.028ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.618m	3.843ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.799m	4.682ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.963m	3.928ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.847m	4.610ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.935m	4.481ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.185m	4.653ms	1	1	100.00
		chip_tap_straps_dev	14.013m	14.198ms	1	1	100.00
		chip_tap_straps_rma	2.000m	2.483ms	1	1	100.00
		chip_tap_straps_prod	9.067m	9.889ms	1	1	100.00
		chip_rv_dm_lc_disabled	4.353m	11.912ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.362m	3.253ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.764m	3.144ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.473m	3.023ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.069m	2.803ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	20.343m	28.327ms	1	1	100.00
		chip_rv_dm_lc_disabled	4.353m	11.912ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	57.054m	46.653ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.040h	50.024ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	7.152m	8.594ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	58.502m	46.261ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	20.343m	28.327ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.291m	2.468ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.094m	2.229ms	1	1	100.00
		rom_volatile_raw_unlock	1.137m	2.527ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	56.477m	16.720ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.139m	19.071ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	10.083m	6.312ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	10.083m	6.312ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	10.083m	6.312ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	5.579m	4.376ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	7.792m	13.143ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	18.591m	22.479ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.579m	4.376ms	1	1	100.00
		chip_sw_keymgr_key_derivation	20.418m	10.026ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.813m	3.681ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.030m	3.006ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	18.591m	22.479ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.579m	4.376ms	1	1	100.00
		chip_sw_keymgr_key_derivation	20.418m	10.026ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.813m	3.681ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.030m	3.006ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	7.792m	13.143ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	4.769m	4.841ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	3.089m	3.097ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.020m	3.005ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.295m	6.099ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	10.558m	7.994ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.139m	6.105ms	1	1	100.00
		chip_sw_lc_ctrl_transition	7.792m	13.143ms	1	1	100.00
		chip_prim_tl_access	1.815m	4.847ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	1.815m	4.847ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	17.273m	8.773ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	4.826m	7.690ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	16.319m	22.957ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.093m	7.731ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	7.602m	8.973ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	6.697m	7.049ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	11.032m	19.603ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	12.589m	13.603ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	9.989m	8.769ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	11.264m	9.313ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.652m	4.596ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	4.826m	7.690ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.542m	3.517ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	34.998m	34.542ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	5.308m	7.293ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	4.699m	4.502ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	24.692m	29.883ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	12.446m	7.671ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	14.046m	9.915ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	23.995m	24.802ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.603m	3.007ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	5.206m	4.411ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	4.742m	9.617ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	4.742m	9.617ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	14.046m	9.915ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	24.692m	29.883ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	5.652m	4.596ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.741m	6.805ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.557m	4.068ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	4.256m	5.269ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	3.766m	4.590ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	19.365m	12.857ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.938m	2.272ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	5.206m	4.411ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	13.782m	7.596ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.716m	4.961ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.673m	4.516ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.765m	3.150ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.030m	3.006ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	4.256m	5.269ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	4.256m	5.269ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	12.503m	12.375ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	13.977m	14.251ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.557m	4.068ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	4.719m	4.483ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.522m	6.165ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	2.000m	2.483ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	4.353m	11.912ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.543m	5.222ms	1	1	100.00
		chip_plic_all_irqs_10	5.347m	3.441ms	1	1	100.00
		chip_plic_all_irqs_20	5.885m	4.560ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	1.968m	3.157ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.439m	3.100ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	37.857m	14.686ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	6.357m	5.822ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.675m	3.879ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.046m	3.432ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.594m	2.851ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	4.813m	3.681ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.584m	4.305ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	5.150m	6.351ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	5.871m	7.485ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	7.683m	6.202ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	5.206m	4.411ms	1	1	100.00
		chip_sw_data_integrity_escalation	7.737m	6.120ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	12.446m	7.671ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	20.192m	22.734ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.221m	3.021ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.594m	4.064ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.518m	4.901ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	20.192m	22.734ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	20.192m	22.734ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	13.110m	10.920ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	13.110m	10.920ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	3.485m	5.733ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	7.281m	18.262ms	1	1	100.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	1.953m	2.716ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.540m	2.897ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	3.667m	3.381ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	4.830m	4.057ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	15.947m	8.324ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.283h	31.506ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	28.013m	12.100ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.313m	2.549ms	1	1	100.00
V2		TOTAL			240	275	87.27
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.584m	3.032ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	2.893m	3.026ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.354h	72.097ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	13.955m	6.132ms	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	16.181m	11.907ms	1	1	100.00
		rom_e2e_jtag_debug_dev	17.370m	11.437ms	1	1	100.00
		rom_e2e_jtag_debug_rma	15.366m	10.908ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.284m	4.204ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.825m	3.369ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.597m	5.360ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	12.763s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.371m	5.540ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.487m	2.385ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	14.878m	6.448ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	12.225m	6.517ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.505m	2.517ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	9.624m	5.081ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.987m	2.521ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	6.482m	5.083ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.183m	5.068ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	5.524m	5.596ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	14.046m	9.915ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	16.181m	11.907ms	1	1	100.00
		rom_e2e_jtag_debug_dev	17.370m	11.437ms	1	1	100.00
		rom_e2e_jtag_debug_rma	15.366m	10.908ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	5.507m	4.566ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	5.206m	4.411ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.345h	38.268ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.345h	38.268ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.842m	4.012ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.518m	4.503ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	49.368m	18.882ms	1	1	100.00
V3		TOTAL			22	23	95.65
	Unmapped tests	chip_sival_flash_info_access	2.891m	2.634ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	7.303m	5.839ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.397m	2.431ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.966m	2.893ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.856m	4.060ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	11.998s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	3.121m	2.871ms	1	1	100.00
		TOTAL			287	325	88.31

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.101593739122943698848583630976595643676885832829755842240854076988702730866555
    Line 639, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.4149182389339004766353148960796363750394780917908015951941262492733570340511
    Line 695, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.8835234563212318405020634072569404325318732565721464672476640686126538363555
    Line 709, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.114927591373120973968502528046701726297125474664590217822284550808078200448782
    Line 787, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.25077066998931778653391369498590326961146752042480838482696198657233600503792
    Line 782, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.10903259404908369834269728045588469068021737100138596320826749907840054108288
    Line 543, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.40836365935035873300609995895715987445437985429627973097367225204232464986806
    Line 537, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.65953912054595860755620798038272354490410102045660710914313227498444717604078
    Line 580, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.81354287731452142776892663387977047404756744604008459202507186218452290786798
    Line 584, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.88896957907532497749114657062080132378413804712301122373965585600370528742891
    Line 608, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.81781504510328626452821487233252115100762863489662011227265553076077070484985
    Line 673, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.26751221381875373567239632002517509951040619214522710946292771936728072965506
    Line 662, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.60122599916254600161832992138078138006776431919270454789576320565792492985930
    Line 755, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.29041381817485569400477065933988353233260527619413107589896037122752893370157
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.145s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.44087567672824244631284907976146294722169980493362099784603478703639609123029
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 3.606s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.71663573489849413879667899444751654983308577716677743129977531553591283679740
    Line 836, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.99575496263160888121341302775405878467985636736652133868419847857067755440438
    Line 795, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.75438439093768522719214708052696010092950552880364968881212332672121214642587
    Line 940, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.20056484321101767513237491567714768936499298935326846996867858447879538200766
    Line 706, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.15739099126405385154140537891200291169851046339373298159625551692265358226758
    Line 446, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3878.879660 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3878.879660 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:529) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@100461) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.95994632248966234308002421592782467436860194413088309160660434848263399118651
Line 446, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 5269.395696 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@100461) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5269.395696 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:197)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.39694850414674697787893920408080591132230392163301996765213497425253672654582
    Line 416, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 10919.550960 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:197)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 10919.550960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.50959750551924763431622949004013155194287202151846968329889123005463701096613
    Line 405, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2258.067548 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 2258.067548 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.24357278511833170479113213266445024203744399985217055658926025341750997481332
    Line 405, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2809.394000 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2809.394000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:586) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.86478495044633547968553589187725155458506954192036024939435670231229896109625
    Line 425, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 2991.152325 us: (cip_base_vseq.sv:586) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 2991.152325 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:529) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32965) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.412441806244539893234066280688770146822119804413364082227680382577865224121
Line 228, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2644.505222 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32965) { a_addr: 'h1063c  a_data: 'h6268a47  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h4  a_opcode: 'h4  a_user: 'h1ba8e  d_param: 'h0  d_source: 'h4  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2644.505222 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.38596848452866703188175779203698948659088751982653670589942720692966029980107
    Line 414, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 2978.892000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2978.892000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.9652744612717712073460027420291459818667376825381409653513336803656774336096
    Line 416, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3083.092000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3083.092000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:128)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.88779113542198285705915707659537479579239905215550941466186468211610812645829
    Line 434, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 18956.511367 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:128)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 18956.511367 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.60872689536105441236429860895925224026150927262037147262245556786510695125756
    Line 673, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.668997459564645913971825514755022175516744334970928706425642789184733275876
    Line 657, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:529) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33127) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.89274851154679860064188547906964199991694677736943360655463798086619232759056
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 1841.719082 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33127) { a_addr: 'h10598  a_data: 'h37ef9cbd  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h30  a_opcode: 'h4  a_user: 'h19210  d_param: 'h0  d_source: 'h30  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1841.719082 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---