ADC_CTRL Simulation Results

Thursday April 10 2025 20:14:43 UTC

GitHub Revision: 66485ba

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	10.220s	5.660ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.370s	1.196ms	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.140s	446.002us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	56.180s	25.708ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.240s	926.960us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.800s	641.531us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.140s	446.002us	1	1	100.00
		adc_ctrl_csr_aliasing	4.240s	926.960us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	7.123m	494.137ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	13.892m	489.396ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	3.155m	168.657ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	4.368m	167.746ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	7.829m	571.742ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	9.303m	599.022ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	4.210m	163.368ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	2.042m	2.000s	0	1	0.00
V2	poweron_counter	adc_ctrl_poweron_counter	2.190s	4.136ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	17.290s	35.885ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	29.800s	60.213ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	15.606m	576.516ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	2.130s	435.455us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.760s	342.544us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.440s	368.129us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.440s	368.129us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.370s	1.196ms	1	1	100.00
		adc_ctrl_csr_rw	2.140s	446.002us	1	1	100.00
		adc_ctrl_csr_aliasing	4.240s	926.960us	1	1	100.00
		adc_ctrl_same_csr_outstanding	4.810s	4.800ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.370s	1.196ms	1	1	100.00
		adc_ctrl_csr_rw	2.140s	446.002us	1	1	100.00
		adc_ctrl_csr_aliasing	4.240s	926.960us	1	1	100.00
		adc_ctrl_same_csr_outstanding	4.810s	4.800ms	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	tl_intg_err	adc_ctrl_sec_cm	3.420s	4.140ms	1	1	100.00
		adc_ctrl_tl_intg_err	14.480s	8.522ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	14.480s	8.522ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	3.590s	1.742ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_clock_gating has 1 failures.

    • 0.adc_ctrl_clock_gating.49054791161884103894406719561714499180172748765359630899115396482042707236709
      Line 163, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest/run.log

        UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---