AES/MASKED Simulation Results

Thursday April 10 2025 20:14:43 UTC

GitHub Revision: 66485ba

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	54.646us	1	1	100.00
V1	smoke	aes_smoke	5.000s	204.987us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	73.140us	1	1	100.00
V1	csr_rw	aes_csr_rw	4.000s	83.924us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	1.488ms	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	473.821us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	65.199us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	83.924us	1	1	100.00
		aes_csr_aliasing	5.000s	473.821us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	5.000s	204.987us	1	1	100.00
		aes_config_error	5.000s	103.582us	1	1	100.00
		aes_stress	6.000s	118.889us	1	1	100.00
V2	key_length	aes_smoke	5.000s	204.987us	1	1	100.00
		aes_config_error	5.000s	103.582us	1	1	100.00
		aes_stress	6.000s	118.889us	1	1	100.00
V2	back2back	aes_stress	6.000s	118.889us	1	1	100.00
		aes_b2b	13.000s	669.853us	1	1	100.00
V2	backpressure	aes_stress	6.000s	118.889us	1	1	100.00
V2	multi_message	aes_smoke	5.000s	204.987us	1	1	100.00
		aes_config_error	5.000s	103.582us	1	1	100.00
		aes_stress	6.000s	118.889us	1	1	100.00
		aes_alert_reset	6.000s	151.162us	1	1	100.00
V2	failure_test	aes_man_cfg_err	5.000s	66.601us	1	1	100.00
		aes_config_error	5.000s	103.582us	1	1	100.00
		aes_alert_reset	6.000s	151.162us	1	1	100.00
V2	trigger_clear_test	aes_clear	6.000s	381.564us	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	11.000s	834.022us	1	1	100.00
V2	reset_recovery	aes_alert_reset	6.000s	151.162us	1	1	100.00
V2	stress	aes_stress	6.000s	118.889us	1	1	100.00
V2	sideload	aes_stress	6.000s	118.889us	1	1	100.00
		aes_sideload	7.000s	811.401us	1	1	100.00
V2	deinitialization	aes_deinit	5.000s	107.804us	1	1	100.00
V2	stress_all	aes_stress_all	26.000s	1.680ms	1	1	100.00
V2	alert_test	aes_alert_test	4.000s	87.612us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	173.998us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	173.998us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	73.140us	1	1	100.00
		aes_csr_rw	4.000s	83.924us	1	1	100.00
		aes_csr_aliasing	5.000s	473.821us	1	1	100.00
		aes_same_csr_outstanding	5.000s	73.597us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	73.140us	1	1	100.00
		aes_csr_rw	4.000s	83.924us	1	1	100.00
		aes_csr_aliasing	5.000s	473.821us	1	1	100.00
		aes_same_csr_outstanding	5.000s	73.597us	1	1	100.00
V2		TOTAL			13	13	100.00
V2S	reseeding	aes_reseed	5.000s	66.895us	1	1	100.00
V2S	fault_inject	aes_fi	6.000s	83.910us	1	1	100.00
		aes_control_fi	5.000s	84.195us	1	1	100.00
		aes_cipher_fi	5.000s	70.827us	1	1	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	88.015us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	88.015us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	88.015us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	88.015us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	286.040us	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	11.000s	1.790ms	1	1	100.00
		aes_tl_intg_err	6.000s	388.948us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	388.948us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	6.000s	151.162us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	88.015us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	5.000s	204.987us	1	1	100.00
		aes_stress	6.000s	118.889us	1	1	100.00
		aes_alert_reset	6.000s	151.162us	1	1	100.00
		aes_core_fi	5.000s	92.909us	1	1	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	88.015us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	5.000s	467.342us	1	1	100.00
		aes_stress	6.000s	118.889us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	6.000s	118.889us	1	1	100.00
		aes_sideload	7.000s	811.401us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	467.342us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	467.342us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	467.342us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	467.342us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	467.342us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	6.000s	118.889us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	6.000s	118.889us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	6.000s	83.910us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	6.000s	83.910us	1	1	100.00
		aes_control_fi	5.000s	84.195us	1	1	100.00
		aes_cipher_fi	5.000s	70.827us	1	1	100.00
		aes_ctr_fi	5.000s	49.719us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	6.000s	83.910us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	6.000s	83.910us	1	1	100.00
		aes_control_fi	5.000s	84.195us	1	1	100.00
		aes_cipher_fi	5.000s	70.827us	1	1	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	5.000s	70.827us	1	1	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	6.000s	83.910us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	6.000s	83.910us	1	1	100.00
		aes_control_fi	5.000s	84.195us	1	1	100.00
		aes_ctr_fi	5.000s	49.719us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	6.000s	83.910us	1	1	100.00
		aes_control_fi	5.000s	84.195us	1	1	100.00
		aes_cipher_fi	5.000s	70.827us	1	1	100.00
		aes_ctr_fi	5.000s	49.719us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	6.000s	151.162us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	6.000s	83.910us	1	1	100.00
		aes_control_fi	5.000s	84.195us	1	1	100.00
		aes_cipher_fi	5.000s	70.827us	1	1	100.00
		aes_ctr_fi	5.000s	49.719us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	6.000s	83.910us	1	1	100.00
		aes_control_fi	5.000s	84.195us	1	1	100.00
		aes_cipher_fi	5.000s	70.827us	1	1	100.00
		aes_ctr_fi	5.000s	49.719us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	6.000s	83.910us	1	1	100.00
		aes_control_fi	5.000s	84.195us	1	1	100.00
		aes_ctr_fi	5.000s	49.719us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	6.000s	83.910us	1	1	100.00
		aes_control_fi	5.000s	84.195us	1	1	100.00
		aes_cipher_fi	5.000s	70.827us	1	1	100.00
V2S		TOTAL			11	11	100.00
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	18.000s	3.843ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			31	32	96.88

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:908) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.58780868341326777083980550382240711479372979482401831863601769575151267241399
      Line 429, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3842688980 ps: (cip_base_vseq.sv:908) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3842688980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---