AES/UNMASKED Simulation Results

Thursday April 10 2025 20:14:43 UTC

GitHub Revision: 66485ba

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	67.907us	1	1	100.00
V1	smoke	aes_smoke	5.000s	55.607us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	135.630us	1	1	100.00
V1	csr_rw	aes_csr_rw	5.000s	92.811us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	590.959us	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	185.760us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	86.726us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	92.811us	1	1	100.00
		aes_csr_aliasing	5.000s	185.760us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	5.000s	55.607us	1	1	100.00
		aes_config_error	5.000s	73.718us	1	1	100.00
		aes_stress	5.000s	236.773us	1	1	100.00
V2	key_length	aes_smoke	5.000s	55.607us	1	1	100.00
		aes_config_error	5.000s	73.718us	1	1	100.00
		aes_stress	5.000s	236.773us	1	1	100.00
V2	back2back	aes_stress	5.000s	236.773us	1	1	100.00
		aes_b2b	6.000s	260.678us	1	1	100.00
V2	backpressure	aes_stress	5.000s	236.773us	1	1	100.00
V2	multi_message	aes_smoke	5.000s	55.607us	1	1	100.00
		aes_config_error	5.000s	73.718us	1	1	100.00
		aes_stress	5.000s	236.773us	1	1	100.00
		aes_alert_reset	5.000s	86.489us	1	1	100.00
V2	failure_test	aes_man_cfg_err	5.000s	67.811us	1	1	100.00
		aes_config_error	5.000s	73.718us	1	1	100.00
		aes_alert_reset	5.000s	86.489us	1	1	100.00
V2	trigger_clear_test	aes_clear	5.000s	63.444us	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	8.000s	203.239us	1	1	100.00
V2	reset_recovery	aes_alert_reset	5.000s	86.489us	1	1	100.00
V2	stress	aes_stress	5.000s	236.773us	1	1	100.00
V2	sideload	aes_stress	5.000s	236.773us	1	1	100.00
		aes_sideload	5.000s	57.482us	1	1	100.00
V2	deinitialization	aes_deinit	5.000s	95.022us	1	1	100.00
V2	stress_all	aes_stress_all	9.000s	779.126us	1	1	100.00
V2	alert_test	aes_alert_test	5.000s	77.206us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	5.000s	518.340us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	5.000s	518.340us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	135.630us	1	1	100.00
		aes_csr_rw	5.000s	92.811us	1	1	100.00
		aes_csr_aliasing	5.000s	185.760us	1	1	100.00
		aes_same_csr_outstanding	4.000s	60.814us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	135.630us	1	1	100.00
		aes_csr_rw	5.000s	92.811us	1	1	100.00
		aes_csr_aliasing	5.000s	185.760us	1	1	100.00
		aes_same_csr_outstanding	4.000s	60.814us	1	1	100.00
V2		TOTAL			13	13	100.00
V2S	reseeding	aes_reseed	4.000s	137.003us	1	1	100.00
V2S	fault_inject	aes_fi	5.000s	143.008us	1	1	100.00
		aes_control_fi	4.000s	47.285us	1	1	100.00
		aes_cipher_fi	16.000s	10.007ms	0	1	0.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	263.105us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	263.105us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	263.105us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	263.105us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	428.722us	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	979.033us	1	1	100.00
		aes_tl_intg_err	5.000s	338.489us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	338.489us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	5.000s	86.489us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	263.105us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	5.000s	55.607us	1	1	100.00
		aes_stress	5.000s	236.773us	1	1	100.00
		aes_alert_reset	5.000s	86.489us	1	1	100.00
		aes_core_fi	5.000s	64.367us	1	1	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	263.105us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	5.000s	53.187us	1	1	100.00
		aes_stress	5.000s	236.773us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	5.000s	236.773us	1	1	100.00
		aes_sideload	5.000s	57.482us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	53.187us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	53.187us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	53.187us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	53.187us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	53.187us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	5.000s	236.773us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	5.000s	236.773us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	5.000s	143.008us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	5.000s	143.008us	1	1	100.00
		aes_control_fi	4.000s	47.285us	1	1	100.00
		aes_cipher_fi	16.000s	10.007ms	0	1	0.00
		aes_ctr_fi	5.000s	290.125us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	5.000s	143.008us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	5.000s	143.008us	1	1	100.00
		aes_control_fi	4.000s	47.285us	1	1	100.00
		aes_cipher_fi	16.000s	10.007ms	0	1	0.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	16.000s	10.007ms	0	1	0.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	5.000s	143.008us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	5.000s	143.008us	1	1	100.00
		aes_control_fi	4.000s	47.285us	1	1	100.00
		aes_ctr_fi	5.000s	290.125us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	5.000s	143.008us	1	1	100.00
		aes_control_fi	4.000s	47.285us	1	1	100.00
		aes_cipher_fi	16.000s	10.007ms	0	1	0.00
		aes_ctr_fi	5.000s	290.125us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	5.000s	86.489us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	5.000s	143.008us	1	1	100.00
		aes_control_fi	4.000s	47.285us	1	1	100.00
		aes_cipher_fi	16.000s	10.007ms	0	1	0.00
		aes_ctr_fi	5.000s	290.125us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	5.000s	143.008us	1	1	100.00
		aes_control_fi	4.000s	47.285us	1	1	100.00
		aes_cipher_fi	16.000s	10.007ms	0	1	0.00
		aes_ctr_fi	5.000s	290.125us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	5.000s	143.008us	1	1	100.00
		aes_control_fi	4.000s	47.285us	1	1	100.00
		aes_ctr_fi	5.000s	290.125us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	5.000s	143.008us	1	1	100.00
		aes_control_fi	4.000s	47.285us	1	1	100.00
		aes_cipher_fi	16.000s	10.007ms	0	1	0.00
V2S		TOTAL			10	11	90.91
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	15.000s	1.576ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			30	32	93.75

Failure Buckets

• UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 1 failures:

  • Test aes_cipher_fi has 1 failures.

    • 0.aes_cipher_fi.107069822814636833259488061031254758786911662155620418147537089929680767166321
      Line 134, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_cipher_fi/latest/run.log

        UVM_FATAL @ 10006582641 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
        UVM_INFO @ 10006582641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:

  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.51058716665057071819064245183738798538744307246524723890838154745255452395663
      Line 1062, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 1576451648 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
        UVM_INFO @ 1576451648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---