CSRNG Simulation Results

Thursday April 10 2025 20:14:43 UTC

GitHub Revision: 66485ba

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	6.000s	18.049us	1	1	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	5.000s	32.067us	1	1	100.00
V1	csr_rw	csrng_csr_rw	5.000s	26.381us	1	1	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	10.000s	218.700us	1	1	100.00
V1	csr_aliasing	csrng_csr_aliasing	7.000s	74.911us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	24.468us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	26.381us	1	1	100.00
		csrng_csr_aliasing	7.000s	74.911us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	interrupts	csrng_intr	6.000s	53.984us	1	1	100.00
V2	alerts	csrng_alert	10.000s	280.534us	1	1	100.00
V2	err	csrng_err	4.000s	25.474us	1	1	100.00
V2	cmds	csrng_cmds	1.150m	3.096ms	1	1	100.00
V2	life cycle	csrng_cmds	1.150m	3.096ms	1	1	100.00
V2	stress_all	csrng_stress_all	3.550m	9.614ms	0	1	0.00
V2	intr_test	csrng_intr_test	6.000s	191.043us	1	1	100.00
V2	alert_test	csrng_alert_test	5.000s	51.006us	1	1	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	6.000s	66.877us	1	1	100.00
V2	tl_d_illegal_access	csrng_tl_errors	6.000s	66.877us	1	1	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	5.000s	32.067us	1	1	100.00
		csrng_csr_rw	5.000s	26.381us	1	1	100.00
		csrng_csr_aliasing	7.000s	74.911us	1	1	100.00
		csrng_same_csr_outstanding	5.000s	16.236us	1	1	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	5.000s	32.067us	1	1	100.00
		csrng_csr_rw	5.000s	26.381us	1	1	100.00
		csrng_csr_aliasing	7.000s	74.911us	1	1	100.00
		csrng_same_csr_outstanding	5.000s	16.236us	1	1	100.00
V2		TOTAL			8	9	88.89
V2S	tl_intg_err	csrng_sec_cm	7.000s	178.519us	1	1	100.00
		csrng_tl_intg_err	10.000s	187.022us	1	1	100.00
V2S	sec_cm_config_regwen	csrng_regwen	4.000s	21.676us	1	1	100.00
		csrng_csr_rw	5.000s	26.381us	1	1	100.00
V2S	sec_cm_config_mubi	csrng_alert	10.000s	280.534us	1	1	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	3.550m	9.614ms	0	1	0.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	6.000s	53.984us	1	1	100.00
		csrng_err	4.000s	25.474us	1	1	100.00
		csrng_sec_cm	7.000s	178.519us	1	1	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	6.000s	53.984us	1	1	100.00
		csrng_err	4.000s	25.474us	1	1	100.00
		csrng_sec_cm	7.000s	178.519us	1	1	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	6.000s	53.984us	1	1	100.00
		csrng_err	4.000s	25.474us	1	1	100.00
		csrng_sec_cm	7.000s	178.519us	1	1	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	6.000s	53.984us	1	1	100.00
		csrng_err	4.000s	25.474us	1	1	100.00
		csrng_sec_cm	7.000s	178.519us	1	1	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	6.000s	53.984us	1	1	100.00
		csrng_err	4.000s	25.474us	1	1	100.00
		csrng_sec_cm	7.000s	178.519us	1	1	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	6.000s	53.984us	1	1	100.00
		csrng_err	4.000s	25.474us	1	1	100.00
		csrng_sec_cm	7.000s	178.519us	1	1	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	6.000s	53.984us	1	1	100.00
		csrng_err	4.000s	25.474us	1	1	100.00
		csrng_sec_cm	7.000s	178.519us	1	1	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	10.000s	280.534us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	6.000s	53.984us	1	1	100.00
		csrng_err	4.000s	25.474us	1	1	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	3.550m	9.614ms	0	1	0.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	10.000s	280.534us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	10.000s	187.022us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	6.000s	53.984us	1	1	100.00
		csrng_err	4.000s	25.474us	1	1	100.00
		csrng_sec_cm	7.000s	178.519us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	6.000s	53.984us	1	1	100.00
		csrng_err	4.000s	25.474us	1	1	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	6.000s	53.984us	1	1	100.00
		csrng_err	4.000s	25.474us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	6.000s	53.984us	1	1	100.00
		csrng_err	4.000s	25.474us	1	1	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	6.000s	53.984us	1	1	100.00
		csrng_err	4.000s	25.474us	1	1	100.00
		csrng_sec_cm	7.000s	178.519us	1	1	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	6.000s	53.984us	1	1	100.00
		csrng_err	4.000s	25.474us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	5.000s	40.470us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			17	19	89.47

Failure Buckets

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:

  • Test csrng_stress_all has 1 failures.

    • 0.csrng_stress_all.60621295182057542879242012695470201404074361929334333312365218930040624819428
      Line 133, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all/latest/run.log

        UVM_ERROR @ 9613821735 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 9613821735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 1 failures:

  • Test csrng_stress_all_with_rand_reset has 1 failures.

    • 0.csrng_stress_all_with_rand_reset.8430652602921231029149510548503326896586120722727807396185162641318341268211
      Line 108, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @  40470441 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
        UVM_INFO @  40470441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---