EDN Simulation Results

Thursday April 10 2025 20:14:43 UTC

GitHub Revision: 66485ba

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.780s	24.751us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.870s	16.261us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.630s	33.432us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	4.430s	338.851us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	2.030s	31.625us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.830s	47.027us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.630s	33.432us	1	1	100.00
		edn_csr_aliasing	2.030s	31.625us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.850s	57.596us	1	1	100.00
V2	csrng_commands	edn_genbits	1.850s	57.596us	1	1	100.00
V2	genbits	edn_genbits	1.850s	57.596us	1	1	100.00
V2	interrupts	edn_intr	1.900s	21.076us	1	1	100.00
V2	alerts	edn_alert	1.820s	30.412us	1	1	100.00
V2	errs	edn_err	1.790s	46.323us	1	1	100.00
V2	disable	edn_disable	1.620s	34.793us	1	1	100.00
		edn_disable_auto_req_mode	1.980s	50.479us	1	1	100.00
V2	stress_all	edn_stress_all	4.030s	1.224ms	1	1	100.00
V2	intr_test	edn_intr_test	1.800s	22.808us	1	1	100.00
V2	alert_test	edn_alert_test	1.740s	12.826us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.640s	305.948us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.640s	305.948us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.870s	16.261us	1	1	100.00
		edn_csr_rw	1.630s	33.432us	1	1	100.00
		edn_csr_aliasing	2.030s	31.625us	1	1	100.00
		edn_same_csr_outstanding	1.970s	123.708us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.870s	16.261us	1	1	100.00
		edn_csr_rw	1.630s	33.432us	1	1	100.00
		edn_csr_aliasing	2.030s	31.625us	1	1	100.00
		edn_same_csr_outstanding	1.970s	123.708us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	5.240s	1.262ms	1	1	100.00
		edn_tl_intg_err	4.130s	202.288us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.850s	17.448us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.820s	30.412us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	5.240s	1.262ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	5.240s	1.262ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	5.240s	1.262ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	5.240s	1.262ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.820s	30.412us	1	1	100.00
		edn_sec_cm	5.240s	1.262ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.820s	30.412us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	4.130s	202.288us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	52.660s	11.207ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00