| V1 |
smoke |
hmac_smoke |
6.570s |
458.220us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
hmac_csr_hw_reset |
1.550s |
45.059us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
hmac_csr_rw |
2.030s |
64.775us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
hmac_csr_bit_bash |
12.330s |
2.952ms |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
hmac_csr_aliasing |
6.300s |
1.252ms |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
hmac_csr_mem_rw_with_rand_reset |
13.183m |
243.562ms |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
hmac_csr_rw |
2.030s |
64.775us |
1 |
1 |
100.00 |
|
|
hmac_csr_aliasing |
6.300s |
1.252ms |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
long_msg |
hmac_long_msg |
11.950s |
1.188ms |
1 |
1 |
100.00 |
| V2 |
back_pressure |
hmac_back_pressure |
49.360s |
3.960ms |
1 |
1 |
100.00 |
| V2 |
test_vectors |
hmac_test_sha256_vectors |
10.250s |
238.669us |
1 |
1 |
100.00 |
|
|
hmac_test_sha384_vectors |
21.030s |
1.674ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha512_vectors |
20.150s |
246.407us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac256_vectors |
9.710s |
1.086ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac384_vectors |
9.950s |
331.212us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac512_vectors |
9.810s |
231.244us |
1 |
1 |
100.00 |
| V2 |
burst_wr |
hmac_burst_wr |
23.040s |
6.916ms |
1 |
1 |
100.00 |
| V2 |
datapath_stress |
hmac_datapath_stress |
10.837m |
9.383ms |
1 |
1 |
100.00 |
| V2 |
error |
hmac_error |
16.580s |
1.023ms |
1 |
1 |
100.00 |
| V2 |
wipe_secret |
hmac_wipe_secret |
1.521m |
11.101ms |
1 |
1 |
100.00 |
| V2 |
save_and_restore |
hmac_smoke |
6.570s |
458.220us |
1 |
1 |
100.00 |
|
|
hmac_long_msg |
11.950s |
1.188ms |
1 |
1 |
100.00 |
|
|
hmac_back_pressure |
49.360s |
3.960ms |
1 |
1 |
100.00 |
|
|
hmac_datapath_stress |
10.837m |
9.383ms |
1 |
1 |
100.00 |
|
|
hmac_burst_wr |
23.040s |
6.916ms |
1 |
1 |
100.00 |
|
|
hmac_stress_all |
1.630m |
12.380ms |
1 |
1 |
100.00 |
| V2 |
fifo_empty_status_interrupt |
hmac_smoke |
6.570s |
458.220us |
1 |
1 |
100.00 |
|
|
hmac_long_msg |
11.950s |
1.188ms |
1 |
1 |
100.00 |
|
|
hmac_back_pressure |
49.360s |
3.960ms |
1 |
1 |
100.00 |
|
|
hmac_datapath_stress |
10.837m |
9.383ms |
1 |
1 |
100.00 |
|
|
hmac_wipe_secret |
1.521m |
11.101ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha256_vectors |
10.250s |
238.669us |
1 |
1 |
100.00 |
|
|
hmac_test_sha384_vectors |
21.030s |
1.674ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha512_vectors |
20.150s |
246.407us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac256_vectors |
9.710s |
1.086ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac384_vectors |
9.950s |
331.212us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac512_vectors |
9.810s |
231.244us |
1 |
1 |
100.00 |
| V2 |
wide_digest_configurable_key_length |
hmac_smoke |
6.570s |
458.220us |
1 |
1 |
100.00 |
|
|
hmac_long_msg |
11.950s |
1.188ms |
1 |
1 |
100.00 |
|
|
hmac_back_pressure |
49.360s |
3.960ms |
1 |
1 |
100.00 |
|
|
hmac_datapath_stress |
10.837m |
9.383ms |
1 |
1 |
100.00 |
|
|
hmac_burst_wr |
23.040s |
6.916ms |
1 |
1 |
100.00 |
|
|
hmac_error |
16.580s |
1.023ms |
1 |
1 |
100.00 |
|
|
hmac_wipe_secret |
1.521m |
11.101ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha256_vectors |
10.250s |
238.669us |
1 |
1 |
100.00 |
|
|
hmac_test_sha384_vectors |
21.030s |
1.674ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha512_vectors |
20.150s |
246.407us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac256_vectors |
9.710s |
1.086ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac384_vectors |
9.950s |
331.212us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac512_vectors |
9.810s |
231.244us |
1 |
1 |
100.00 |
|
|
hmac_stress_all |
1.630m |
12.380ms |
1 |
1 |
100.00 |
| V2 |
stress_all |
hmac_stress_all |
1.630m |
12.380ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
hmac_alert_test |
1.390s |
13.723us |
1 |
1 |
100.00 |
| V2 |
intr_test |
hmac_intr_test |
1.610s |
13.075us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
hmac_tl_errors |
3.020s |
195.869us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
hmac_tl_errors |
3.020s |
195.869us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
hmac_csr_hw_reset |
1.550s |
45.059us |
1 |
1 |
100.00 |
|
|
hmac_csr_rw |
2.030s |
64.775us |
1 |
1 |
100.00 |
|
|
hmac_csr_aliasing |
6.300s |
1.252ms |
1 |
1 |
100.00 |
|
|
hmac_same_csr_outstanding |
1.960s |
23.131us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
hmac_csr_hw_reset |
1.550s |
45.059us |
1 |
1 |
100.00 |
|
|
hmac_csr_rw |
2.030s |
64.775us |
1 |
1 |
100.00 |
|
|
hmac_csr_aliasing |
6.300s |
1.252ms |
1 |
1 |
100.00 |
|
|
hmac_same_csr_outstanding |
1.960s |
23.131us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
17 |
17 |
100.00 |
| V2S |
tl_intg_err |
hmac_sec_cm |
1.750s |
99.549us |
1 |
1 |
100.00 |
|
|
hmac_tl_intg_err |
2.410s |
190.625us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
hmac_tl_intg_err |
2.410s |
190.625us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
write_config_and_secret_key_during_msg_wr |
hmac_smoke |
6.570s |
458.220us |
1 |
1 |
100.00 |
| V3 |
stress_reset |
hmac_stress_reset |
4.260s |
362.151us |
1 |
1 |
100.00 |
| V3 |
stress_all_with_rand_reset |
hmac_stress_all_with_rand_reset |
21.050s |
6.545ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
2 |
2 |
100.00 |
|
Unmapped tests |
hmac_directed |
2.830s |
35.631us |
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
28 |
28 |
100.00 |