I2C Simulation Results

Thursday April 10 2025 20:14:43 UTC

GitHub Revision: `66485ba`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	49.960s	17.342ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	10.870s	1.986ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.490s	54.678us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.720s	49.038us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.750s	65.773us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.210s	417.020us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.560s	136.694us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.720s	49.038us	1	1	100.00
		i2c_csr_aliasing	2.210s	417.020us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	3.910s	405.433us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	1.336m	4.756ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	14.260s	3.125ms	1	1	100.00
V2	host_override	i2c_host_override	1.630s	201.327us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.580m	27.984ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	26.650s	10.760ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.940s	596.209us	1	1	100.00
		i2c_host_fifo_fmt_empty	16.630s	9.102ms	1	1	100.00
		i2c_host_fifo_reset_rx	5.840s	140.432us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.098m	2.681ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	12.440s	2.060ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.320s	345.724us	1	1	100.00
V2	target_glitch	i2c_target_glitch	8.230s	7.685ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	3.008m	45.023ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.740s	1.464ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	12.380s	5.193ms	1	1	100.00
		i2c_target_intr_smoke	4.480s	1.600ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.840s	177.897us	1	1	100.00
		i2c_target_fifo_reset_tx	1.860s	236.851us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	44.870s	40.804ms	1	1	100.00
		i2c_target_stress_rd	12.380s	5.193ms	1	1	100.00
		i2c_target_intr_stress_wr	1.253m	21.516ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.530s	8.122ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	28.850s	2.409ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	5.310s	2.221ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.680s	349.359us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.630s	2.035ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.800s	219.531us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	14.260s	3.125ms	1	1	100.00
		i2c_host_perf_precise	2.220s	77.530us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	12.440s	2.060ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	3.320s	226.565us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.160s	505.827us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.780s	1.028ms	1	1	100.00
		i2c_target_nack_txstretch	2.310s	573.748us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	16.530s	2.207ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.540s	931.878us	1	1	100.00
V2	alert_test	i2c_alert_test	1.700s	38.709us	1	1	100.00
V2	intr_test	i2c_intr_test	1.640s	16.812us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.200s	146.017us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.200s	146.017us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.490s	54.678us	1	1	100.00
		i2c_csr_rw	1.720s	49.038us	1	1	100.00
		i2c_csr_aliasing	2.210s	417.020us	1	1	100.00
		i2c_same_csr_outstanding	1.770s	28.395us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.490s	54.678us	1	1	100.00
		i2c_csr_rw	1.720s	49.038us	1	1	100.00
		i2c_csr_aliasing	2.210s	417.020us	1	1	100.00
		i2c_same_csr_outstanding	1.770s	28.395us	1	1	100.00
V2		TOTAL			37	38	97.37
V2S	tl_intg_err	i2c_tl_intg_err	1.980s	70.789us	1	1	100.00
		i2c_sec_cm	2.000s	84.865us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.980s	70.789us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	4.980s	210.772us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.570s	658.954us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	13.830s	4.171ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			46	50	92.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:907) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.27041605573301451730313970657369411021203157765696379539446456033876507954885
    Line 81, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 210772056 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 210772056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.56653940485232499768098999862049528823319018996216175827735574735274273773708
    Line 88, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4171028868 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4171028868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.54629128780091828013186603992889171666018069489607648529192514440346940621651
Line 200, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 4756228514 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @623468

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.114855861218563826005619328372375765886725912974219058046479382498916505477200
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 658954071 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 94 [0x5e])
  UVM_INFO @ 658954071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```