KMAC/MASKED Simulation Results

Thursday April 10 2025 20:14:43 UTC

GitHub Revision: 66485ba

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	9.220s	526.028us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.860s	37.043us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.720s	49.732us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	11.080s	1.272ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	5.980s	140.208us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.180s	46.971us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.720s	49.732us	1	1	100.00
		kmac_csr_aliasing	5.980s	140.208us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.670s	49.436us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.990s	61.702us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	2.922m	6.736ms	1	1	100.00
V2	burst_write	kmac_burst_write	5.989m	18.600ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	30.180s	3.141ms	1	1	100.00
		kmac_test_vectors_sha3_256	32.740s	2.527ms	1	1	100.00
		kmac_test_vectors_sha3_384	20.240s	4.033ms	1	1	100.00
		kmac_test_vectors_sha3_512	13.568m	9.954ms	1	1	100.00
		kmac_test_vectors_shake_128	3.292m	17.746ms	1	1	100.00
		kmac_test_vectors_shake_256	29.416m	60.704ms	1	1	100.00
		kmac_test_vectors_kmac	3.130s	85.089us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.320s	86.530us	1	1	100.00
V2	sideload	kmac_sideload	14.420s	256.410us	1	1	100.00
V2	app	kmac_app	1.192m	3.796ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.601m	16.474ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	3.205m	36.191ms	1	1	100.00
V2	error	kmac_error	38.490s	2.087ms	1	1	100.00
V2	key_error	kmac_key_error	2.530s	2.796ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.620s	329.797us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	2.070s	81.001us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.620s	12.663us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	42.190s	3.542ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.040s	43.853us	1	1	100.00
V2	stress_all	kmac_stress_all	10.281m	120.905ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.670s	147.793us	1	1	100.00
V2	alert_test	kmac_alert_test	1.780s	39.275us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.890s	169.038us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.890s	169.038us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.860s	37.043us	1	1	100.00
		kmac_csr_rw	1.720s	49.732us	1	1	100.00
		kmac_csr_aliasing	5.980s	140.208us	1	1	100.00
		kmac_same_csr_outstanding	2.810s	143.964us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.860s	37.043us	1	1	100.00
		kmac_csr_rw	1.720s	49.732us	1	1	100.00
		kmac_csr_aliasing	5.980s	140.208us	1	1	100.00
		kmac_same_csr_outstanding	2.810s	143.964us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.910s	76.935us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.910s	76.935us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.910s	76.935us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.910s	76.935us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.860s	304.336us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	38.510s	5.210ms	1	1	100.00
		kmac_tl_intg_err	3.040s	109.403us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.040s	109.403us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.040s	43.853us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	9.220s	526.028us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	14.420s	256.410us	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.910s	76.935us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	38.510s	5.210ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	38.510s	5.210ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	38.510s	5.210ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	9.220s	526.028us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.040s	43.853us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	38.510s	5.210ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.281m	36.685ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	9.220s	526.028us	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	21.130s	4.484ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.106598582701022519911052991606774990068284401062805908220252168726947878052838
      Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffff03ff) == (exp_vals[4] & 'hffff03ff)))'
        UVM_ERROR @ 304336217 ps: (kmac_csr_assert_fpv.sv:487) [ASSERT FAILED] entropy_period_rd_A
        UVM_INFO @ 304336217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---