KMAC/UNMASKED Simulation Results

Thursday April 10 2025 20:14:43 UTC

GitHub Revision: 66485ba

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	23.410s	8.269ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.810s	63.800us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.890s	44.898us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	7.450s	503.415us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.210s	1.451ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.700s	59.390us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.890s	44.898us	1	1	100.00
		kmac_csr_aliasing	4.210s	1.451ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.510s	35.528us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.420s	35.336us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	5.668m	21.326ms	1	1	100.00
V2	burst_write	kmac_burst_write	6.837m	67.427ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	26.563m	189.007ms	1	1	100.00
		kmac_test_vectors_sha3_256	22.920m	163.529ms	1	1	100.00
		kmac_test_vectors_sha3_384	20.890s	1.211ms	1	1	100.00
		kmac_test_vectors_sha3_512	13.981m	296.854ms	1	1	100.00
		kmac_test_vectors_shake_128	2.206m	32.917ms	1	1	100.00
		kmac_test_vectors_shake_256	23.507m	80.521ms	1	1	100.00
		kmac_test_vectors_kmac	2.890s	278.581us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.510s	295.363us	1	1	100.00
V2	sideload	kmac_sideload	4.311m	18.219ms	1	1	100.00
V2	app	kmac_app	23.050s	567.787us	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.398m	52.682ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	3.766m	72.848ms	1	1	100.00
V2	error	kmac_error	2.524m	19.754ms	1	1	100.00
V2	key_error	kmac_key_error	1.990s	662.673us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	1.793m	10.095ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	4.570s	106.354us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	6.250s	110.448us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	3.650s	671.790us	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	3.070s	42.181us	1	1	100.00
V2	stress_all	kmac_stress_all	3.399m	16.105ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.640s	65.908us	1	1	100.00
V2	alert_test	kmac_alert_test	1.790s	33.992us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.560s	211.492us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.560s	211.492us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.810s	63.800us	1	1	100.00
		kmac_csr_rw	1.890s	44.898us	1	1	100.00
		kmac_csr_aliasing	4.210s	1.451ms	1	1	100.00
		kmac_same_csr_outstanding	2.450s	125.080us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.810s	63.800us	1	1	100.00
		kmac_csr_rw	1.890s	44.898us	1	1	100.00
		kmac_csr_aliasing	4.210s	1.451ms	1	1	100.00
		kmac_same_csr_outstanding	2.450s	125.080us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.350s	99.251us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.350s	99.251us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.350s	99.251us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.350s	99.251us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.040s	32.622us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	34.000s	3.508ms	1	1	100.00
		kmac_tl_intg_err	3.580s	431.832us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.580s	431.832us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	3.070s	42.181us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	23.410s	8.269ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	4.311m	18.219ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.350s	99.251us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	34.000s	3.508ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	34.000s	3.508ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	34.000s	3.508ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	23.410s	8.269ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	3.070s	42.181us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	34.000s	3.508ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.553m	14.787ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	23.410s	8.269ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	37.950s	9.808ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			37	40	92.50

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.57940009914500014074344708296121411217209259984407351412284484175213255991584
      Line 93, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10094994369 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xfbd2c000, Comparison=CompareOpEq, exp_data=0x1, call_count=19)
        UVM_INFO @ 10094994369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.5783023382796429413452480634056671973561563653061686691791326617341337897990
      Line 142, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9807977954 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 9807977954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.96070264717379518691958955824411929267545833308449507891942852420160035867805
      Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[40] & 'hffffffff)))'
        UVM_ERROR @  32622030 ps: (kmac_csr_assert_fpv.sv:497) [ASSERT FAILED] prefix_1_rd_A
        UVM_INFO @  32622030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---