ROM_CTRL/64KB Simulation Results

Thursday April 10 2025 20:14:43 UTC

GitHub Revision: 66485ba

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 7.340s 394.501us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 9.660s 1.188ms 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 7.340s 294.566us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 7.750s 214.483us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 8.420s 533.710us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.590s 387.413us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 7.340s 294.566us 1 1 100.00
rom_ctrl_csr_aliasing 8.420s 533.710us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 6.890s 276.124us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 6.760s 1.071ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 9.060s 570.363us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 18.840s 1.096ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 15.110s 568.514us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 8.020s 1.025ms 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 9.200s 758.475us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 9.200s 758.475us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 9.660s 1.188ms 1 1 100.00
rom_ctrl_csr_rw 7.340s 294.566us 1 1 100.00
rom_ctrl_csr_aliasing 8.420s 533.710us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.980s 533.856us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 9.660s 1.188ms 1 1 100.00
rom_ctrl_csr_rw 7.340s 294.566us 1 1 100.00
rom_ctrl_csr_aliasing 8.420s 533.710us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.980s 533.856us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.322m 1.957ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 38.470s 6.381ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.578m 751.796us 1 1 100.00
rom_ctrl_tl_intg_err 1.148m 1.097ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.578m 751.796us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.578m 751.796us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.322m 1.957ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.322m 1.957ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.322m 1.957ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.322m 1.957ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.322m 1.957ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.578m 751.796us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.578m 751.796us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 7.340s 394.501us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 7.340s 394.501us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 7.340s 394.501us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.148m 1.097ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.322m 1.957ms 1 1 100.00
rom_ctrl_kmac_err_chk 15.110s 568.514us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.322m 1.957ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.322m 1.957ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.322m 1.957ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 38.470s 6.381ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.578m 751.796us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 2.185m 19.918ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00