RV_DM/USE_JTAG_INTERFACE Simulation Results

Thursday April 10 2025 20:14:43 UTC

GitHub Revision: 66485ba

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 20.590s 11.943ms 0 1 0.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 1.450s 489.623us 1 1 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 2.560s 456.628us 1 1 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 6.580s 6.586ms 1 1 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 2.140s 869.401us 1 1 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 8.090s 10.659ms 1 1 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 8.130s 3.109ms 1 1 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 5.510s 15.397ms 1 1 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 1.621m 49.865ms 1 1 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 1.870s 435.188us 1 1 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 1.910s 649.441us 1 1 100.00
V1 cmderr_exception rv_dm_cmderr_exception 1.850s 162.998us 1 1 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 1.890s 536.055us 1 1 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 2.440s 383.330us 1 1 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 2.240s 453.518us 1 1 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.770s 400.188us 1 1 100.00
V1 halt_resume rv_dm_halt_resume_whereto 2.290s 1.108ms 1 1 100.00
V1 progbuf_busy rv_dm_cmderr_busy 1.870s 435.188us 1 1 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 2.390s 261.240us 1 1 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 3.620s 928.478us 1 1 100.00
V1 progbuf_exception rv_dm_cmderr_exception 1.850s 162.998us 1 1 100.00
V1 rom_read_access rv_dm_rom_read_access 1.660s 111.460us 1 1 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 3.000s 565.402us 1 1 100.00
V1 csr_rw rv_dm_csr_rw 2.810s 392.562us 1 1 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 38.820s 1.435ms 1 1 100.00
V1 csr_aliasing rv_dm_csr_aliasing 51.790s 10.184ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 1.760s 45.134us 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 51.790s 10.184ms 1 1 100.00
rv_dm_csr_rw 2.810s 392.562us 1 1 100.00
V1 mem_walk rv_dm_mem_walk 1.540s 34.291us 1 1 100.00
V1 mem_partial_access rv_dm_mem_partial_access 1.480s 26.629us 1 1 100.00
V1 TOTAL 25 27 92.59
V2 idcode rv_dm_smoke 20.590s 11.943ms 0 1 0.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 1.700s 216.429us 1 1 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.670s 88.954us 1 1 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 1.740s 153.010us 1 1 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 1.840s 497.619us 1 1 100.00
V2 sba rv_dm_sba_tl_access 4.630s 2.564ms 1 1 100.00
rv_dm_delayed_resp_sba_tl_access 1.750s 130.069us 0 1 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 21.120s 16.138ms 1 1 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 9.550s 7.745ms 1 1 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 2.010s 265.327us 1 1 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 2.350s 1.834ms 1 1 100.00
V2 ndmreset_req rv_dm_ndmreset_req 1.910s 260.952us 1 1 100.00
V2 hart_unavail rv_dm_hart_unavail 1.640s 56.910us 1 1 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 6.950s 4.266ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 1.510s 42.261us 0 1 0.00
V2 hartsel_warl rv_dm_hartsel_warl 1.630s 249.858us 1 1 100.00
V2 stress_all rv_dm_stress_all 4.530s 1.100ms 1 1 100.00
V2 alert_test rv_dm_alert_test 1.680s 47.693us 1 1 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 1.560s 51.730us 0 1 0.00
V2 tl_d_illegal_access rv_dm_tl_errors 1.560s 51.730us 0 1 0.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 51.790s 10.184ms 1 1 100.00
rv_dm_csr_hw_reset 3.000s 565.402us 1 1 100.00
rv_dm_csr_rw 2.810s 392.562us 1 1 100.00
rv_dm_same_csr_outstanding 4.130s 166.366us 1 1 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 51.790s 10.184ms 1 1 100.00
rv_dm_csr_hw_reset 3.000s 565.402us 1 1 100.00
rv_dm_csr_rw 2.810s 392.562us 1 1 100.00
rv_dm_same_csr_outstanding 4.130s 166.366us 1 1 100.00
V2 TOTAL 16 19 84.21
V2S tl_intg_err rv_dm_sec_cm 2.120s 914.278us 1 1 100.00
rv_dm_tl_intg_err 6.740s 1.022ms 1 1 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 6.740s 1.022ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 2.350s 1.834ms 1 1 100.00
rv_dm_debug_disabled 1.760s 159.357us 1 1 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 2.350s 1.834ms 1 1 100.00
rv_dm_debug_disabled 1.760s 159.357us 1 1 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 20.590s 11.943ms 0 1 0.00
V2S sec_cm_dm_en_ctrl_lc_gated rv_dm_buffered_enable 1.850s 341.781us 1 1 100.00
V2S sec_cm_sba_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.690s 58.788us 1 1 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.690s 58.788us 1 1 100.00
V2S sec_cm_exec_ctrl_mubi rv_dm_buffered_enable 1.850s 341.781us 1 1 100.00
V2S TOTAL 5 5 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 1.560s 17.484us 0 1 0.00
V3 TOTAL 0 1 0.00
Unmapped tests rv_dm_scanmode 1.490s 104.952us 1 1 100.00
TOTAL 47 53 88.68

Failure Buckets