RV_TIMER Simulation Results

Thursday April 10 2025 20:14:43 UTC

GitHub Revision: 66485ba

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	5.153m	109.061ms	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.460s	18.481us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.610s	17.595us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.070s	667.663us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.720s	36.329us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.990s	476.677us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.610s	17.595us	1	1	100.00
		rv_timer_csr_aliasing	1.720s	36.329us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	45.010s	75.372ms	1	1	100.00
V2	disabled	rv_timer_disabled	2.716m	560.629ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	9.890s	7.460ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	9.890s	7.460ms	1	1	100.00
V2	stress	rv_timer_stress_all	2.357m	184.360ms	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.530s	49.849us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.950s	797.292us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.950s	797.292us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.460s	18.481us	1	1	100.00
		rv_timer_csr_rw	1.610s	17.595us	1	1	100.00
		rv_timer_csr_aliasing	1.720s	36.329us	1	1	100.00
		rv_timer_same_csr_outstanding	2.070s	33.137us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.460s	18.481us	1	1	100.00
		rv_timer_csr_rw	1.610s	17.595us	1	1	100.00
		rv_timer_csr_aliasing	1.720s	36.329us	1	1	100.00
		rv_timer_same_csr_outstanding	2.070s	33.137us	1	1	100.00
V2		TOTAL			7	7	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.680s	397.845us	1	1	100.00
		rv_timer_tl_intg_err	1.960s	654.644us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.960s	654.644us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	7.850s	5.807ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			15	16	93.75

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:907) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test rv_timer_stress_all_with_rand_reset has 1 failures.

    • 0.rv_timer_stress_all_with_rand_reset.104777989540297021865951938271460910449445722334523912729007468253209957895422
      Line 105, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5807495047 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5807495047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---