SPI_DEVICE/1R1W Simulation Results

Thursday April 10 2025 20:14:43 UTC

GitHub Revision: 66485ba

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	37.830s	31.845ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.100s	180.625us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.670s	318.728us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	16.750s	6.533ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	10.490s	864.888us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.360s	323.784us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.670s	318.728us	1	1	100.00
		spi_device_csr_aliasing	10.490s	864.888us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.410s	20.286us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.890s	58.383us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.910s	53.072us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.710s	2.922us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.570s	3.606us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.750s	48.522us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.750s	48.522us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	3.130s	861.856us	1	1	100.00
		spi_device_tpm_sts_read	1.830s	38.302us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	39.160s	44.513ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	2.720s	264.129us	1	1	100.00
		spi_device_flash_all	2.378m	29.299ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	3.970s	604.619us	1	1	100.00
		spi_device_flash_all	2.378m	29.299ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	3.970s	604.619us	1	1	100.00
		spi_device_flash_all	2.378m	29.299ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	2.378m	29.299ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	7.340s	4.418ms	1	1	100.00
		spi_device_flash_all	2.378m	29.299ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	7.340s	4.418ms	1	1	100.00
		spi_device_flash_all	2.378m	29.299ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	7.340s	4.418ms	1	1	100.00
		spi_device_flash_all	2.378m	29.299ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	7.340s	4.418ms	1	1	100.00
		spi_device_flash_all	2.378m	29.299ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	7.340s	4.418ms	1	1	100.00
		spi_device_flash_all	2.378m	29.299ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	6.850s	1.950ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	1.358m	47.935ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.358m	47.935ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.358m	47.935ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	7.100s	157.126us	1	1	100.00
		spi_device_read_buffer_direct	6.980s	3.742ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.358m	47.935ms	1	1	100.00
		spi_device_flash_all	2.378m	29.299ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	2.378m	29.299ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	2.378m	29.299ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	8.270s	3.496ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	8.270s	3.496ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	37.830s	31.845ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	3.821m	67.209ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.105m	17.830ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.560s	13.677us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.550s	24.318us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.120s	342.676us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.120s	342.676us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.100s	180.625us	1	1	100.00
		spi_device_csr_rw	2.670s	318.728us	1	1	100.00
		spi_device_csr_aliasing	10.490s	864.888us	1	1	100.00
		spi_device_same_csr_outstanding	3.690s	632.793us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.100s	180.625us	1	1	100.00
		spi_device_csr_rw	2.670s	318.728us	1	1	100.00
		spi_device_csr_aliasing	10.490s	864.888us	1	1	100.00
		spi_device_same_csr_outstanding	3.690s	632.793us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.210s	107.680us	1	1	100.00
		spi_device_tl_intg_err	12.210s	708.363us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	12.210s	708.363us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.900s	134.211us	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.4308614714489584086596321805803286569750780902342589155044569087765607056253
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1799547 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[99])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1799547 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1799547 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[995])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.26842657109129704661956204545206612518694227773330198863793429353084767655840
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   2835504 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   2835504 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   2907504 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x26e52d [1001101110010100101101] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   2907504 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0x26e52d [1001101110010100101101] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])