SPI_DEVICE/2P Simulation Results

Thursday April 10 2025 20:14:43 UTC

GitHub Revision: 66485ba

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	3.599m	38.088ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.190s	185.912us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.020s	22.522us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	9.970s	911.662us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	6.600s	1.389ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.750s	226.285us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.020s	22.522us	1	1	100.00
		spi_device_csr_aliasing	6.600s	1.389ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.570s	11.670us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.330s	40.167us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.590s	15.074us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.820s	188.933us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	1.710s	1.707us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.960s	460.998us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.960s	460.998us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	3.050s	1.020ms	1	1	100.00
		spi_device_tpm_sts_read	1.730s	128.458us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	13.750s	20.281ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	2.650s	30.652us	1	1	100.00
		spi_device_flash_all	1.640s	10.559us	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	3.040s	261.620us	1	1	100.00
		spi_device_flash_all	1.640s	10.559us	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	3.040s	261.620us	1	1	100.00
		spi_device_flash_all	1.640s	10.559us	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.640s	10.559us	1	1	100.00
V2	cmd_read_status	spi_device_intercept	7.600s	647.811us	1	1	100.00
		spi_device_flash_all	1.640s	10.559us	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	7.600s	647.811us	1	1	100.00
		spi_device_flash_all	1.640s	10.559us	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	7.600s	647.811us	1	1	100.00
		spi_device_flash_all	1.640s	10.559us	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	7.600s	647.811us	1	1	100.00
		spi_device_flash_all	1.640s	10.559us	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	7.600s	647.811us	1	1	100.00
		spi_device_flash_all	1.640s	10.559us	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	3.190s	562.042us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	2.590s	109.551us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.590s	109.551us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.590s	109.551us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	11.890s	14.624ms	1	1	100.00
		spi_device_read_buffer_direct	3.300s	608.354us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.590s	109.551us	1	1	100.00
		spi_device_flash_all	1.640s	10.559us	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.640s	10.559us	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.640s	10.559us	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.700s	75.189us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.700s	75.189us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	3.599m	38.088ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	5.822m	228.589ms	1	1	100.00
V2	stress_all	spi_device_stress_all	2.752m	104.106ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.600s	33.218us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.590s	12.908us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.760s	55.084us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.760s	55.084us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.190s	185.912us	1	1	100.00
		spi_device_csr_rw	2.020s	22.522us	1	1	100.00
		spi_device_csr_aliasing	6.600s	1.389ms	1	1	100.00
		spi_device_same_csr_outstanding	2.230s	96.738us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.190s	185.912us	1	1	100.00
		spi_device_csr_rw	2.020s	22.522us	1	1	100.00
		spi_device_csr_aliasing	6.600s	1.389ms	1	1	100.00
		spi_device_same_csr_outstanding	2.230s	96.738us	1	1	100.00
V2		TOTAL			21	22	95.45
V2S	tl_intg_err	spi_device_sec_cm	2.050s	212.741us	1	1	100.00
		spi_device_tl_intg_err	11.380s	608.655us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	11.380s	608.655us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	4.109m	492.593ms	1	1	100.00
		TOTAL			32	33	96.97

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:
  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.82605468100524090291868780032170606203703007790217744406802912953432442582699
      Line 71, in log /nightly/runs/scratch/master/spi_device_2p-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @    876264 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    876264 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @    880264 ps: (spi_device_ram_cfg_vseq.sv:23) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === dst_ram_cfg (0x5b4c22 [10110110100110000100010] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @    880264 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)