SPI_HOST Simulation Results

Thursday April 10 2025 20:14:43 UTC

GitHub Revision: 66485ba

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	1.267m	6.768ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	18.142us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	60.220us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	541.050us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	96.435us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	38.378us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	60.220us	1	1	100.00
		spi_host_csr_aliasing	4.000s	96.435us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	13.921us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	112.388us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	4.000s	60.314us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	6.000s	828.350us	1	1	100.00
		spi_host_error_cmd	4.000s	17.030us	1	1	100.00
		spi_host_event	6.000s	312.615us	1	1	100.00
V2	clock_rate	spi_host_speed	13.000s	339.201us	1	1	100.00
V2	speed	spi_host_speed	13.000s	339.201us	1	1	100.00
V2	chip_select_timing	spi_host_speed	13.000s	339.201us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	44.000s	1.756ms	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	519.338us	1	1	100.00
V2	cpol_cpha	spi_host_speed	13.000s	339.201us	1	1	100.00
V2	full_cycle	spi_host_speed	13.000s	339.201us	1	1	100.00
V2	duplex	spi_host_smoke	1.267m	6.768ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	1.267m	6.768ms	1	1	100.00
V2	stress_all	spi_host_stress_all	7.000s	92.159us	1	1	100.00
V2	spien	spi_host_spien	12.000s	3.418ms	1	1	100.00
V2	stall	spi_host_status_stall	17.000s	1.211ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	5.000s	38.119us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	6.000s	828.350us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	62.635us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	21.791us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	306.341us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	306.341us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	18.142us	1	1	100.00
		spi_host_csr_rw	4.000s	60.220us	1	1	100.00
		spi_host_csr_aliasing	4.000s	96.435us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	29.256us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	18.142us	1	1	100.00
		spi_host_csr_rw	4.000s	60.220us	1	1	100.00
		spi_host_csr_aliasing	4.000s	96.435us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	29.256us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	307.734us	1	1	100.00
		spi_host_sec_cm	4.000s	219.930us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	307.734us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	3.917m	6.217ms	1	1	100.00
		TOTAL			26	26	100.00