SRAM_CTRL/MAIN Simulation Results

Thursday April 10 2025 20:14:43 UTC

GitHub Revision: 66485ba

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 7.320s 734.530us 1 1 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 1.630s 14.427us 1 1 100.00
V1 csr_rw sram_ctrl_csr_rw 1.710s 22.300us 1 1 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.580s 175.167us 1 1 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 1.660s 14.623us 1 1 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 3.810s 1.411ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 1.710s 22.300us 1 1 100.00
sram_ctrl_csr_aliasing 1.660s 14.623us 1 1 100.00
V1 mem_walk sram_ctrl_mem_walk 2.986m 14.071ms 1 1 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 55.740s 1.415ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 multiple_keys sram_ctrl_multiple_keys 7.100m 12.936ms 1 1 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 3.094m 3.599ms 1 1 100.00
V2 bijection sram_ctrl_bijection 12.160m 85.547ms 1 1 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 8.636m 41.700ms 1 1 100.00
V2 lc_escalation sram_ctrl_lc_escalation 21.440s 5.062ms 1 1 100.00
V2 executable sram_ctrl_executable 7.016m 16.460ms 1 1 100.00
V2 partial_access sram_ctrl_partial_access 13.940s 1.189ms 1 1 100.00
sram_ctrl_partial_access_b2b 5.318m 36.477ms 1 1 100.00
V2 max_throughput sram_ctrl_max_throughput 21.950s 754.961us 1 1 100.00
sram_ctrl_throughput_w_partial_write 4.490s 4.426ms 1 1 100.00
sram_ctrl_throughput_w_readback 28.420s 800.024us 1 1 100.00
V2 regwen sram_ctrl_regwen 3.105m 10.831ms 1 1 100.00
V2 ram_cfg sram_ctrl_ram_cfg 4.450s 692.655us 1 1 100.00
V2 stress_all sram_ctrl_stress_all 1.182h 240.918ms 1 1 100.00
V2 alert_test sram_ctrl_alert_test 1.700s 14.566us 1 1 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 3.090s 273.087us 1 1 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 3.090s 273.087us 1 1 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 1.630s 14.427us 1 1 100.00
sram_ctrl_csr_rw 1.710s 22.300us 1 1 100.00
sram_ctrl_csr_aliasing 1.660s 14.623us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.800s 27.138us 1 1 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 1.630s 14.427us 1 1 100.00
sram_ctrl_csr_rw 1.710s 22.300us 1 1 100.00
sram_ctrl_csr_aliasing 1.660s 14.623us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.800s 27.138us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 19.220s 7.692ms 1 1 100.00
V2S tl_intg_err sram_ctrl_sec_cm 1.810s 2.026us 0 1 0.00
sram_ctrl_tl_intg_err 2.390s 330.029us 1 1 100.00
V2S prim_count_check sram_ctrl_sec_cm 1.810s 2.026us 0 1 0.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.390s 330.029us 1 1 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 3.105m 10.831ms 1 1 100.00
V2S sec_cm_readback_config_regwen sram_ctrl_regwen 3.105m 10.831ms 1 1 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 1.710s 22.300us 1 1 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 7.016m 16.460ms 1 1 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 7.016m 16.460ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 7.016m 16.460ms 1 1 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 21.440s 5.062ms 1 1 100.00
V2S sec_cm_prim_ram_ctrl_mubi sram_ctrl_mubi_enc_err 4.570s 1.484ms 1 1 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 19.220s 7.692ms 1 1 100.00
V2S sec_cm_mem_readback sram_ctrl_readback_err 5.370s 1.352ms 1 1 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 7.320s 734.530us 1 1 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 7.320s 734.530us 1 1 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 7.016m 16.460ms 1 1 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 1.810s 2.026us 0 1 0.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 21.440s 5.062ms 1 1 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 1.810s 2.026us 0 1 0.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 1.810s 2.026us 0 1 0.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 7.320s 734.530us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 1.810s 2.026us 0 1 0.00
V2S TOTAL 4 5 80.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 52.030s 14.019ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 30 31 96.77

Failure Buckets