SRAM_CTRL/RET Simulation Results

Thursday April 10 2025 20:14:43 UTC

GitHub Revision: 66485ba

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.630s	80.402us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.380s	76.196us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.510s	38.791us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.980s	30.678us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.630s	38.807us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.900s	29.962us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.510s	38.791us	1	1	100.00
		sram_ctrl_csr_aliasing	1.630s	38.807us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	8.800s	6.210ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.930s	167.950us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	15.193m	19.083ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	4.222m	4.005ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	55.830s	14.410ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	10.633m	16.571ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	5.660s	1.018ms	1	1	100.00
V2	executable	sram_ctrl_executable	5.132m	8.894ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	15.230s	4.116ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.716m	52.143ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	32.280s	275.781us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	5.890s	71.863us	1	1	100.00
		sram_ctrl_throughput_w_readback	13.920s	160.797us	1	1	100.00
V2	regwen	sram_ctrl_regwen	7.099m	19.655ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.680s	178.565us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	14.942m	9.513ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.800s	42.551us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.620s	79.054us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.620s	79.054us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.380s	76.196us	1	1	100.00
		sram_ctrl_csr_rw	1.510s	38.791us	1	1	100.00
		sram_ctrl_csr_aliasing	1.630s	38.807us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.590s	35.238us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.380s	76.196us	1	1	100.00
		sram_ctrl_csr_rw	1.510s	38.791us	1	1	100.00
		sram_ctrl_csr_aliasing	1.630s	38.807us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.590s	35.238us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.050s	428.076us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.700s	6.460us	0	1	0.00
		sram_ctrl_tl_intg_err	2.360s	249.948us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.700s	6.460us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.360s	249.948us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	7.099m	19.655ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	7.099m	19.655ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.510s	38.791us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	5.132m	8.894ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	5.132m	8.894ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	5.132m	8.894ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	5.660s	1.018ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.900s	24.740us	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.050s	428.076us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.810s	52.285us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.630s	80.402us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.630s	80.402us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	5.132m	8.894ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.700s	6.460us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	5.660s	1.018ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.700s	6.460us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.700s	6.460us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.630s	80.402us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.700s	6.460us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	34.550s	15.386ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.42920937293566677102879300147042059339847572121674108874914010833873014573004
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  24740398 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  24740398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.36322543047207905883585461861281232241458171906037043041881274135349934060414
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   6459511 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   6459511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---