SYSRST_CTRL Simulation Results

Thursday April 10 2025 20:14:43 UTC

GitHub Revision: 66485ba

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	3.000s	2.116ms	1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	2.780s	2.499ms	1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	2.590s	2.442ms	1	1	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	2.590s	2.566ms	1	1	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	12.890s	6.034ms	1	1	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	5.850s	2.054ms	1	1	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	1.956m	40.586ms	1	1	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	6.650s	2.477ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	2.500s	2.097ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	5.850s	2.054ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	6.650s	2.477ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	1.691m	108.638ms	1	1	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	1.016m	32.135ms	1	1	100.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	6.860s	3.105ms	1	1	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	2.050s	3.185ms	1	1	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	4.590s	2.521ms	1	1	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	5.280s	2.196ms	1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	8.770s	4.254ms	1	1	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	4.510s	2.621ms	1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	5.340s	4.168ms	1	1	100.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	1.254m	38.540ms	1	1	100.00
V2	stress_all	sysrst_ctrl_stress_all	15.920s	124.052ms	0	1	0.00
V2	alert_test	sysrst_ctrl_alert_test	4.930s	2.010ms	1	1	100.00
V2	intr_test	sysrst_ctrl_intr_test	4.910s	2.013ms	1	1	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	5.970s	2.075ms	1	1	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	5.970s	2.075ms	1	1	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	12.890s	6.034ms	1	1	100.00
		sysrst_ctrl_csr_rw	5.850s	2.054ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	6.650s	2.477ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	8.060s	7.606ms	1	1	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	12.890s	6.034ms	1	1	100.00
		sysrst_ctrl_csr_rw	5.850s	2.054ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	6.650s	2.477ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	8.060s	7.606ms	1	1	100.00
V2		TOTAL			14	15	93.33
V2S	tl_intg_err	sysrst_ctrl_sec_cm	12.700s	22.076ms	1	1	100.00
		sysrst_ctrl_tl_intg_err	42.190s	22.232ms	1	1	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	42.190s	22.232ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	10.160s	4.822ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:251) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 1 failures:
  • Test sysrst_ctrl_stress_all has 1 failures.

    • 0.sysrst_ctrl_stress_all.40401271989997859641063395780729516157761686495519741347163730165726101043842
      Line 388, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 124051685562 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_ERROR @ 124051732436 ps: (cip_base_scoreboard.sv:263) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
        UVM_INFO @ 124051732436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---