UART Simulation Results

Thursday April 10 2025 20:14:43 UTC

GitHub Revision: 66485ba

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	5.760s	5.775ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	2.840s	1.031ms	1	1	100.00
V1	csr_rw	uart_csr_rw	1.560s	30.678us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.350s	319.768us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.620s	15.423us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.640s	17.921us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.560s	30.678us	1	1	100.00
		uart_csr_aliasing	1.620s	15.423us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	6.020s	6.014ms	1	1	100.00
V2	parity	uart_smoke	5.760s	5.775ms	1	1	100.00
		uart_tx_rx	6.020s	6.014ms	1	1	100.00
V2	parity_error	uart_intr	17.800s	61.657ms	1	1	100.00
		uart_rx_parity_err	16.660s	33.220ms	1	1	100.00
V2	watermark	uart_tx_rx	6.020s	6.014ms	1	1	100.00
		uart_intr	17.800s	61.657ms	1	1	100.00
V2	fifo_full	uart_fifo_full	8.840s	71.757ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	34.210s	117.937ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	1.651m	124.609ms	1	1	100.00
V2	rx_frame_err	uart_intr	17.800s	61.657ms	1	1	100.00
V2	rx_break_err	uart_intr	17.800s	61.657ms	1	1	100.00
V2	rx_timeout	uart_intr	17.800s	61.657ms	1	1	100.00
V2	perf	uart_perf	3.669m	10.826ms	1	1	100.00
V2	sys_loopback	uart_loopback	3.250s	1.562ms	1	1	100.00
V2	line_loopback	uart_loopback	3.250s	1.562ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	1.203m	52.309ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.580s	4.947ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.730s	1.578ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	17.320s	2.957ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	3.317m	83.237ms	1	1	100.00
V2	stress_all	uart_stress_all	1.665m	101.467ms	1	1	100.00
V2	alert_test	uart_alert_test	1.460s	28.222us	1	1	100.00
V2	intr_test	uart_intr_test	1.530s	12.571us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.050s	80.050us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.050s	80.050us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	2.840s	1.031ms	1	1	100.00
		uart_csr_rw	1.560s	30.678us	1	1	100.00
		uart_csr_aliasing	1.620s	15.423us	1	1	100.00
		uart_same_csr_outstanding	1.750s	297.118us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	2.840s	1.031ms	1	1	100.00
		uart_csr_rw	1.560s	30.678us	1	1	100.00
		uart_csr_aliasing	1.620s	15.423us	1	1	100.00
		uart_same_csr_outstanding	1.750s	297.118us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	2.050s	195.176us	1	1	100.00
		uart_tl_intg_err	2.220s	98.081us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.220s	98.081us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	16.290s	1.667ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00