CHIP Simulation Results

Thursday April 10 2025 20:14:43 UTC

GitHub Revision: `66485ba`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.755m	2.779ms	1	1	100.00
		chip_sw_example_rom	56.700s	2.176ms	1	1	100.00
		chip_sw_example_manufacturer	2.713m	2.730ms	1	1	100.00
		chip_sw_example_concurrency	2.207m	3.315ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	2.272m	4.152ms	1	1	100.00
V1	csr_rw	chip_csr_rw	3.183m	3.944ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	5.494m	5.792ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	54.231m	28.131ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	56.680s	2.656ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	54.231m	28.131ms	1	1	100.00
		chip_csr_rw	3.183m	3.944ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	6.420s	211.699us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.503m	4.407ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.503m	4.407ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.503m	4.407ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.891m	4.735ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.891m	4.735ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.342m	4.115ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.307m	4.008ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.288m	4.345ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	5.795m	4.502ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	5.262m	3.910ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	10.448m	9.467ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.196m	4.928ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.196m	4.928ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.919m	2.768ms	0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	3.279m	6.027ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.401m	4.554ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	6.166m	6.201ms	1	1	100.00
		chip_tap_straps_testunlock0	4.320m	5.680ms	1	1	100.00
		chip_tap_straps_rma	2.287m	3.058ms	1	1	100.00
		chip_tap_straps_prod	1.878m	2.857ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.218m	3.365ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	12.610m	9.463ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.192m	5.127ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.192m	5.127ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	9.754m	7.721ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	38.823m	24.048ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.504m	4.610ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.168m	5.769ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.737m	18.741ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.871m	2.859ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.959m	6.645ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	1.976m	2.234ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	16.323m	9.003ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.676m	3.310ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.653m	5.516ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.889m	3.050ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.019m	3.029ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	9.652m	9.479ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.537m	5.274ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.024m	3.155ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.537m	5.274ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.239m	2.226ms	1	1	100.00
		chip_sw_aes_smoketest	2.695m	2.637ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.159m	3.415ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.718m	3.107ms	1	1	100.00
		chip_sw_csrng_smoketest	1.760m	2.710ms	1	1	100.00
		chip_sw_entropy_src_smoketest	5.949m	3.642ms	1	1	100.00
		chip_sw_gpio_smoketest	3.124m	3.050ms	1	1	100.00
		chip_sw_hmac_smoketest	3.378m	2.904ms	1	1	100.00
		chip_sw_kmac_smoketest	3.009m	3.015ms	1	1	100.00
		chip_sw_otbn_smoketest	16.214m	9.159ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.468m	5.224ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.290m	5.234ms	1	1	100.00
		chip_sw_rv_plic_smoketest	1.910m	2.817ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.498m	2.748ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.228m	3.231ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.156m	2.464ms	1	1	100.00
		chip_sw_uart_smoketest	1.949m	2.730ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.262m	2.274ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	5.010m	4.009ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.937h	60.906ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	39.277m	14.730ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.680m	6.493ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	2.897m	3.081ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.594m	3.660ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.731h	53.308ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.868h	56.754ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	51.910s	1.763ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	51.910s	1.763ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	54.231m	28.131ms	1	1	100.00
		chip_same_csr_outstanding	34.433m	28.039ms	1	1	100.00
		chip_csr_hw_reset	2.272m	4.152ms	1	1	100.00
		chip_csr_rw	3.183m	3.944ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	54.231m	28.131ms	1	1	100.00
		chip_same_csr_outstanding	34.433m	28.039ms	1	1	100.00
		chip_csr_hw_reset	2.272m	4.152ms	1	1	100.00
		chip_csr_rw	3.183m	3.944ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	27.240s	443.353us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	6.550s	43.937us	1	1	100.00
		xbar_smoke_large_delays	59.520s	9.837ms	1	1	100.00
		xbar_smoke_slow_rsp	47.600s	5.459ms	1	1	100.00
		xbar_random_zero_delays	33.170s	620.939us	1	1	100.00
		xbar_random_large_delays	58.590s	9.917ms	1	1	100.00
		xbar_random_slow_rsp	1.540m	10.881ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	18.510s	267.474us	1	1	100.00
		xbar_error_and_unmapped_addr	15.410s	545.330us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	11.310s	200.724us	1	1	100.00
		xbar_error_and_unmapped_addr	15.410s	545.330us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	16.400s	395.394us	1	1	100.00
		xbar_access_same_device_slow_rsp	2.735m	19.818ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	10.940s	515.569us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	3.815m	11.530ms	1	1	100.00
		xbar_stress_all_with_error	1.276m	1.794ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	1.388m	545.980us	1	1	100.00
		xbar_stress_all_with_reset_error	2.912m	3.657ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	39.277m	14.730ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	34.406m	26.733ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	36.284m	15.271ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	31.453m	10.476ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	41.182m	15.718ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	39.087m	15.571ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	39.503m	15.220ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	41.355m	15.113ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	27.960s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	27.650s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	27.390s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	27.510s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	27.500s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	27.000s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	28.260s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	27.180s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	27.140s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	27.410s	10.280us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	26.030s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	25.270s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	29.310s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	25.610s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	24.810s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	26.070s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	25.560s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	24.750s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	25.350s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	27.810s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	26.060s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	25.320s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	24.930s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	28.480s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	27.560s	10.240us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	29.582m	11.152ms	1	1	100.00
		rom_e2e_asm_init_dev	38.488m	15.322ms	1	1	100.00
		rom_e2e_asm_init_prod	38.224m	15.911ms	1	1	100.00
		rom_e2e_asm_init_prod_end	37.623m	15.740ms	1	1	100.00
		rom_e2e_asm_init_rma	34.922m	14.522ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	36.003m	15.068ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	35.790m	14.796ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	37.364m	15.284ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	38.427m	16.025ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	5.507m	18.652ms	1	1	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	5.507m	18.652ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.662m	3.289ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.871m	2.859ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.801m	3.279ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.368m	2.631ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	25.909m	12.362ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.377m	2.386ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.213m	4.486ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	5.888m	6.007ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	7.912m	5.537ms	1	1	100.00
		chip_plic_all_irqs_10	4.004m	4.021ms	1	1	100.00
		chip_plic_all_irqs_20	5.527m	4.150ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	3.569m	3.252ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	16.530m	12.847ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.578m	4.072ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.583m	3.453ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	9.867m	10.495ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	13.538m	6.366ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	17.072m	8.682ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	11.471m	7.436ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	1.929h	255.099ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.370m	3.705ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.468m	5.224ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.370m	3.705ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.806m	10.086ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.806m	10.086ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.630m	6.558ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	5.457m	4.614ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.521m	5.618ms	1	1	100.00
		chip_sw_aes_idle	2.368m	2.631ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.799m	3.490ms	1	1	100.00
		chip_sw_kmac_idle	2.198m	2.914ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.627m	3.438ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	5.772m	4.017ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.934m	5.685ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	5.562m	5.124ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	11.090m	11.475ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.886m	4.100ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.088m	4.980ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.726m	3.858ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.077m	5.402ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.589m	4.296ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.081m	4.979ms	1	1	100.00
		chip_sw_ast_clk_outputs	9.754m	7.721ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	5.474m	7.332ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.726m	3.858ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.077m	5.402ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.504m	4.610ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.168m	5.769ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.737m	18.741ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.871m	2.859ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.959m	6.645ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	1.976m	2.234ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	16.323m	9.003ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.676m	3.310ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.653m	5.516ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.889m	3.050ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.147m	2.621ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	5.437m	5.158ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	9.904m	6.654ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	49.191m	25.615ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.070m	3.324ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.347m	2.553ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	10.359m	8.035ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.955m	2.840ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.785m	6.117ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	15.482m	22.226ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	54.481m	33.953ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	9.754m	7.721ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.650m	5.172ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.829m	2.508ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	5.888m	6.007ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	13.538m	6.366ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	13.053m	6.607ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	1.871m	2.329ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	7.471m	7.840ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.128m	2.439ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	55.239m	21.861ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.578m	2.670ms	1	1	100.00
		chip_sw_edn_entropy_reqs	9.494m	6.946ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.578m	2.670ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	13.053m	6.607ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.683m	2.935ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	15.552m	18.003ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.436m	5.507ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.168m	5.769ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.045m	4.156ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.504m	4.610ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	55.782m	43.086ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	15.552m	18.003ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.023m	3.509ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	13.860m	7.818ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.808m	4.706ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	55.782m	43.086ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.808m	4.706ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.808m	4.706ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	3.808m	4.706ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.808m	4.706ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	5.888m	6.007ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	2.177m	5.599ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.084m	4.908ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.850m	5.953ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.850m	5.953ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	1.972m	3.102ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	1.976m	2.234ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.799m	3.490ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.572m	3.414ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	13.448m	6.632ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.456m	5.514ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	6.275m	4.229ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	5.170m	4.124ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	3.986m	3.321ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	13.860m	7.818ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	16.323m	9.003ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	20.114m	9.563ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	25.909m	12.362ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	37.284m	11.088ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.584m	2.488ms	1	1	100.00
		chip_sw_kmac_mode_kmac	3.028m	2.793ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.676m	3.310ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	13.860m	7.818ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	6.824m	10.931ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.670m	2.931ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	20.130m	9.202ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.198m	2.914ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.213m	4.486ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	6.166m	6.201ms	1	1	100.00
		chip_tap_straps_rma	2.287m	3.058ms	1	1	100.00
		chip_tap_straps_prod	1.878m	2.857ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.932m	2.968ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	6.824m	10.931ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	6.824m	10.931ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	6.824m	10.931ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	9.221m	5.833ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	3.808m	4.706ms	1	1	100.00
		chip_sw_flash_rma_unlocked	55.782m	43.086ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.435m	3.377ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.846m	7.057ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	9.164m	7.256ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.351m	5.397ms	1	1	100.00
		chip_sw_lc_ctrl_transition	6.824m	10.931ms	1	1	100.00
		chip_sw_keymgr_key_derivation	13.860m	7.818ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.091m	9.256ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	9.208m	8.627ms	1	1	100.00
		chip_prim_tl_access	2.177m	5.599ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	5.474m	7.332ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.886m	4.100ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.088m	4.980ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.726m	3.858ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.077m	5.402ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.589m	4.296ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.081m	4.979ms	1	1	100.00
		chip_tap_straps_dev	6.166m	6.201ms	1	1	100.00
		chip_tap_straps_rma	2.287m	3.058ms	1	1	100.00
		chip_tap_straps_prod	1.878m	2.857ms	1	1	100.00
		chip_rv_dm_lc_disabled	4.858m	13.268ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.661m	3.503ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.659m	3.275ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.621m	3.296ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	31.550m	27.029ms	0	1	0.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	21.910m	26.562ms	1	1	100.00
		chip_rv_dm_lc_disabled	4.858m	13.268ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.083h	50.329ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.002h	49.010ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	7.442m	7.592ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.056h	47.695ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	21.910m	26.562ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	59.070s	1.795ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.106m	2.335ms	1	1	100.00
		rom_volatile_raw_unlock	1.122m	1.947ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	53.952m	17.331ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.737m	18.741ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.521m	5.618ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.521m	5.618ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.521m	5.618ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.310m	3.391ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	6.824m	10.931ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	15.552m	18.003ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.310m	3.391ms	1	1	100.00
		chip_sw_keymgr_key_derivation	13.860m	7.818ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.711m	4.580ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.873m	3.069ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	15.552m	18.003ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.310m	3.391ms	1	1	100.00
		chip_sw_keymgr_key_derivation	13.860m	7.818ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.711m	4.580ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.873m	3.069ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	6.824m	10.931ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	4.087m	4.222ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.932m	2.968ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.435m	3.377ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.846m	7.057ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	9.164m	7.256ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.351m	5.397ms	1	1	100.00
		chip_sw_lc_ctrl_transition	6.824m	10.931ms	1	1	100.00
		chip_prim_tl_access	2.177m	5.599ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	2.177m	5.599ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	17.162m	9.391ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	4.741m	9.419ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	15.386m	23.697ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.742m	6.927ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	5.773m	7.504ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	6.865m	7.069ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	14.209m	24.084ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	9.094m	9.614ms	0	1	0.00
		chip_sw_aon_timer_wdog_bite_reset	8.806m	10.086ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	10.303m	8.075ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	6.560m	5.609ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	4.741m	9.419ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	4.564m	3.928ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	31.207m	34.092ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.109m	6.308ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	4.443m	4.874ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	24.296m	26.137ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.523m	7.784ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	13.109m	12.925ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	22.063m	24.954ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.233m	2.910ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	5.888m	6.007ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.091m	9.256ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.091m	9.256ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	13.109m	12.925ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	24.296m	26.137ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	6.560m	5.609ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.468m	5.224ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.326m	3.154ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	2.815m	3.527ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	3.899m	3.346ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	16.530m	12.847ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.131m	2.533ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	5.888m	6.007ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	17.072m	8.682ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.397m	5.152ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.760m	5.077ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.469m	2.685ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	1.873m	3.069ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	2.815m	3.527ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	2.815m	3.527ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	7.917m	9.034ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	14.295m	13.436ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.326m	3.154ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	5.366m	4.184ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	3.682m	4.918ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	2.287m	3.058ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	4.858m	13.268ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	7.912m	5.537ms	1	1	100.00
		chip_plic_all_irqs_10	4.004m	4.021ms	1	1	100.00
		chip_plic_all_irqs_20	5.527m	4.150ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.799m	3.350ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.801m	2.841ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	39.277m	14.730ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	5.411m	5.683ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.850m	3.010ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	2.585m	3.355ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.160m	3.517ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	5.711m	4.580ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.653m	5.516ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	7.797m	8.599ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	6.801m	7.279ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	9.208m	8.627ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	5.888m	6.007ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.192m	5.127ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.523m	7.784ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	18.803m	23.770ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.264m	2.772ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.105m	3.557ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	4.951m	4.603ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	18.803m	23.770ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	18.803m	23.770ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	11.854m	11.149ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	11.854m	11.149ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.304m	5.009ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	5.507m	18.652ms	1	1	100.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	1.596m	2.314ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.537m	2.618ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	3.528m	3.479ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.824m	3.992ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	17.300m	8.702ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.221h	32.178ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	28.222m	12.287ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.262m	3.010ms	1	1	100.00
V2		TOTAL			237	275	86.18
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.844m	2.313ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.710m	2.622ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.370h	71.757ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	6.037m	3.817ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	16.659m	11.385ms	1	1	100.00
		rom_e2e_jtag_debug_dev	17.309m	11.038ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.995m	12.234ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	3.186m	3.929ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.590m	3.645ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.567m	4.418ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	15.485s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.520m	5.408ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.703m	2.810ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	15.954m	6.553ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	16.311m	7.657ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.517m	2.634ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.871m	5.455ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.383m	2.464ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	5.446m	4.721ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	4.025m	6.468ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	3.881m	4.992ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	13.109m	12.925ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	16.659m	11.385ms	1	1	100.00
		rom_e2e_jtag_debug_dev	17.309m	11.038ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.995m	12.234ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	4.613m	4.748ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	5.888m	6.007ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.394h	38.510ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.394h	38.510ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.844m	3.325ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.891m	4.735ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	44.968m	18.454ms	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	1.973m	2.915ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	4.940m	5.021ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.466m	2.612ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.362m	3.402ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	4.674m	4.660ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	11.464s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.955m	3.277ms	1	1	100.00
		TOTAL			283	325	87.08

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.7537803473882693687561802062089005848205426100893046650973443628404395918967
    Line 685, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.72951825889520558822016597980683132426153649285751815816417419094499147395271
    Line 705, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.14340406238140222209625027054946196113360831900503161728254558295952135973734
    Line 757, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.47601427587788134892892510358995733630902712283400378189291241640698962430317
    Line 723, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.48507362860918985255083777933219194481297928951971816987035357052108710570631
    Line 644, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.106776342586507452974962287093056534665710229709991673722692813044816193778416
    Line 649, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.52427752981702476001482000692974492104097415955337666472606867234727559538387
    Line 660, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.36612652875639741774676255810269622511581967963140377199759878980351745006897
    Line 661, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.63345108442774399482106539456993817074561036009405374418320330977660492124630
    Line 758, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.99855500498931874855757688026568906169665270424260249613871977542117501223995
    Line 727, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.67384233905342527356348801512763494205325134700174172905740434779226877931637
    Line 624, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.16475337205540485388234395337385154024317610701631209788555748169722541145129
    Line 725, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.105075926676666364189910875261238412977952212583442555221123706097698359336447
    Line 754, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.74981803649866454722299700945945895270358686546182295854707872620650615538006
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.146s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.29386229118217592326392201388141957604398425561755069924337182505532188449611
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 5.480s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.107734337682483897479296096353660710311445284157811445403409263395567353178643
    Line 811, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.87645642885747976750290729998868565550025132844046308311628611463276369457224
    Line 639, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.38064015252734165462571946007669857444833216456967116005598077455437862374573
    Line 888, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.28183122797262609158542488986430660113394944106953772338418254184924341391499
    Line 659, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] has 1 failures:
- Test chip_sw_sleep_pin_mio_dio_val has 1 failures.
  - 0.chip_sw_sleep_pin_mio_dio_val.3216767067177114373684632440251110772879365920487669267936336716486917824024
    Line 714, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_mio_dio_val/latest/run.log
```
  UVM_ERROR @ 2768.000000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
  UVM_INFO @ 2768.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.73561855313341377625383589889174694820111940304835844713024009498609865508882
    Line 419, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3009.852270 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3009.852270 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:820) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] max attempt reached to get lc status LcExtClockSwitched! has 1 failures:
- Test chip_sw_lc_ctrl_rand_to_scrap has 1 failures.
  - 0.chip_sw_lc_ctrl_rand_to_scrap.107387677604028950949841405733247511594163275588513315282887925680498559849637
    Line 411, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_rand_to_scrap/latest/run.log
```
  UVM_FATAL @ 27028.862208 us: (chip_sw_base_vseq.sv:820) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] max attempt reached to get lc status LcExtClockSwitched!
  UVM_INFO @ 27028.862208 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:529) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@78341) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.38475924651263147268578306519024416508332174436875721502200550328565694851507
Line 434, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 3526.526484 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@78341) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3526.526484 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(pend_req[h2d.a_source].pend == *)' has 1 failures:
- Test chip_sw_pwrmgr_deep_sleep_all_reset_reqs has 1 failures.
  - 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.62685324959131584061988727303045148863086304045962930701244280379233453687885
    Line 442, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log
```
      Offending '(pend_req[h2d.a_source].pend == 0)'
  UVM_ERROR @ 9614.183870 us: (tlul_assert.sv:268) [ASSERT FAILED] pendingReqPerSrc_M
  UVM_INFO @ 9614.183870 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:197)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.61973745902646830158445343779601096029173729086386004366670829206675161298845
    Line 419, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 11148.617596 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:197)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 11148.617596 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.13238725103391125901905949604096481092670457040758893350463796992419010090586
    Line 404, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2385.922550 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 2385.922550 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.51954048715593130249841709603533488729179750827655266728074936530119655878142
    Line 405, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3453.176700 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 3453.176700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:586) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.58585609808733042459753184493905167817660470936528870504020644586548074091260
    Line 414, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 2329.193523 us: (cip_base_vseq.sv:586) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 2329.193523 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:529) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32307) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.7266574284159713132150055469544940034052143627376168083028004413850187851829
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 1762.872088 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32307) { a_addr: 'h104d0  a_data: 'hb8e89184  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h22  a_opcode: 'h4  a_user: 'h1a92d  d_param: 'h0  d_source: 'h22  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1762.872088 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.55313971841000125719002681793343860360777074656929590154299285267193440534826
    Line 423, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3081.272000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3081.272000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.11048605785151450293444599548084735261908221416933391186646745331481387777874
    Line 427, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3659.988000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3659.988000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:128)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.28692810037158684422662128747904097695054754627986268112891221018297229193211
    Line 444, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 24048.288780 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:128)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 24048.288780 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.6630964359456137497180008809766942789628356151045707326631976484557257981637
    Line 462, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3817.006408 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3817.006408 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.92489543684260628692612523970593454765690114477719036685905287708251214475336
    Line 779, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.90013227410197587207910593146958056810584638525016671205286775825906902171050
    Line 641, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:529) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32179) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.41169178750801118818488303005787442713260542081670387194661137894861985292775
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2655.700810 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32179) { a_addr: 'h106f0  a_data: 'hc994303a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h28  a_opcode: 'h4  a_user: 'h1bafe  d_param: 'h0  d_source: 'h28  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2655.700810 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---