ADC_CTRL Simulation Results

Monday April 14 2025 20:20:50 UTC

GitHub Revision: 71732d1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	6.490s	5.966ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.430s	1.190ms	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.600s	554.173us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	54.390s	37.516ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.330s	640.070us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.110s	407.354us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.600s	554.173us	1	1	100.00
		adc_ctrl_csr_aliasing	2.330s	640.070us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	7.239m	501.222ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	3.111m	494.817ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	9.412m	326.364ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	14.681m	495.321ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	4.093m	522.064ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	10.687m	406.885ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	2.128m	329.855ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	4.697m	501.190ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	10.430s	5.485ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	38.860s	45.373ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	24.380s	124.296ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	6.008m	209.839ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	2.430s	479.614us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.760s	338.641us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.010s	430.473us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.010s	430.473us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.430s	1.190ms	1	1	100.00
		adc_ctrl_csr_rw	2.600s	554.173us	1	1	100.00
		adc_ctrl_csr_aliasing	2.330s	640.070us	1	1	100.00
		adc_ctrl_same_csr_outstanding	5.110s	4.747ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.430s	1.190ms	1	1	100.00
		adc_ctrl_csr_rw	2.600s	554.173us	1	1	100.00
		adc_ctrl_csr_aliasing	2.330s	640.070us	1	1	100.00
		adc_ctrl_same_csr_outstanding	5.110s	4.747ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	4.850s	8.056ms	1	1	100.00
		adc_ctrl_tl_intg_err	5.900s	8.252ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	5.900s	8.252ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	11.890s	12.705ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00