EDN Simulation Results

Monday April 14 2025 20:20:50 UTC

GitHub Revision: 71732d1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.790s 41.167us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.900s 27.005us 1 1 100.00
V1 csr_rw edn_csr_rw 2.350s 23.582us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 5.670s 516.702us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.970s 36.458us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.230s 23.681us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 2.350s 23.582us 1 1 100.00
edn_csr_aliasing 1.970s 36.458us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 2.050s 150.533us 1 1 100.00
V2 csrng_commands edn_genbits 2.050s 150.533us 1 1 100.00
V2 genbits edn_genbits 2.050s 150.533us 1 1 100.00
V2 interrupts edn_intr 1.700s 30.738us 1 1 100.00
V2 alerts edn_alert 1.940s 27.914us 1 1 100.00
V2 errs edn_err 1.590s 42.302us 1 1 100.00
V2 disable edn_disable 2.030s 12.460us 1 1 100.00
edn_disable_auto_req_mode 2.340s 85.378us 1 1 100.00
V2 stress_all edn_stress_all 5.340s 304.326us 1 1 100.00
V2 intr_test edn_intr_test 1.600s 49.413us 1 1 100.00
V2 alert_test edn_alert_test 1.840s 11.613us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 2.560s 33.257us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 2.560s 33.257us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.900s 27.005us 1 1 100.00
edn_csr_rw 2.350s 23.582us 1 1 100.00
edn_csr_aliasing 1.970s 36.458us 1 1 100.00
edn_same_csr_outstanding 1.920s 35.872us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.900s 27.005us 1 1 100.00
edn_csr_rw 2.350s 23.582us 1 1 100.00
edn_csr_aliasing 1.970s 36.458us 1 1 100.00
edn_same_csr_outstanding 1.920s 35.872us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 4.600s 1.387ms 1 1 100.00
edn_tl_intg_err 2.260s 82.574us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 2.200s 71.048us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 1.940s 27.914us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 4.600s 1.387ms 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 4.600s 1.387ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 4.600s 1.387ms 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 4.600s 1.387ms 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.940s 27.914us 1 1 100.00
edn_sec_cm 4.600s 1.387ms 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.940s 27.914us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.260s 82.574us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets