ENTROPY_SRC Simulation Results

Monday April 14 2025 20:20:50 UTC

GitHub Revision: 71732d1

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 5.000s 61.300us 1 1 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 4.000s 18.743us 1 1 100.00
V1 csr_rw entropy_src_csr_rw 4.000s 37.441us 1 1 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 14.000s 3.190ms 1 1 100.00
V1 csr_aliasing entropy_src_csr_aliasing 6.000s 142.776us 1 1 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 5.000s 88.505us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 4.000s 37.441us 1 1 100.00
entropy_src_csr_aliasing 6.000s 142.776us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware entropy_src_smoke 5.000s 61.300us 1 1 100.00
entropy_src_rng 7.000s 672.572us 0 1 0.00
entropy_src_fw_ov 1.050m 3.273ms 0 1 0.00
V2 firmware_mode entropy_src_fw_ov 1.050m 3.273ms 0 1 0.00
V2 rng_mode entropy_src_rng 7.000s 672.572us 0 1 0.00
V2 rng_max_rate entropy_src_rng_max_rate 4.000s 5.913us 0 1 0.00
V2 health_checks entropy_src_rng 7.000s 672.572us 0 1 0.00
V2 conditioning entropy_src_rng 7.000s 672.572us 0 1 0.00
V2 interrupts entropy_src_rng 7.000s 672.572us 0 1 0.00
entropy_src_intr 5.000s 198.821us 1 1 100.00
V2 alerts entropy_src_rng 7.000s 672.572us 0 1 0.00
entropy_src_functional_alerts 5.000s 134.695us 1 1 100.00
V2 stress_all entropy_src_stress_all 3.133m 10.157ms 1 1 100.00
V2 functional_errors entropy_src_functional_errors 5.000s 62.900us 1 1 100.00
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 16.000s 1.177ms 1 1 100.00
V2 intr_test entropy_src_intr_test 4.000s 19.277us 1 1 100.00
V2 alert_test entropy_src_alert_test 4.000s 49.952us 1 1 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 6.000s 49.900us 1 1 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 6.000s 49.900us 1 1 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 4.000s 18.743us 1 1 100.00
entropy_src_csr_rw 4.000s 37.441us 1 1 100.00
entropy_src_csr_aliasing 6.000s 142.776us 1 1 100.00
entropy_src_same_csr_outstanding 5.000s 261.230us 1 1 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 4.000s 18.743us 1 1 100.00
entropy_src_csr_rw 4.000s 37.441us 1 1 100.00
entropy_src_csr_aliasing 6.000s 142.776us 1 1 100.00
entropy_src_same_csr_outstanding 5.000s 261.230us 1 1 100.00
V2 TOTAL 9 12 75.00
V2S tl_intg_err entropy_src_sec_cm 5.000s 173.288us 1 1 100.00
entropy_src_tl_intg_err 5.000s 479.303us 1 1 100.00
V2S sec_cm_config_regwen entropy_src_rng 7.000s 672.572us 0 1 0.00
entropy_src_cfg_regwen 5.000s 72.394us 1 1 100.00
V2S sec_cm_config_mubi entropy_src_rng 7.000s 672.572us 0 1 0.00
V2S sec_cm_config_redun entropy_src_rng 7.000s 672.572us 0 1 0.00
V2S sec_cm_intersig_mubi entropy_src_rng 7.000s 672.572us 0 1 0.00
entropy_src_fw_ov 1.050m 3.273ms 0 1 0.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 5.000s 62.900us 1 1 100.00
entropy_src_sec_cm 5.000s 173.288us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 5.000s 62.900us 1 1 100.00
entropy_src_sec_cm 5.000s 173.288us 1 1 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 7.000s 672.572us 0 1 0.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 5.000s 62.900us 1 1 100.00
entropy_src_sec_cm 5.000s 173.288us 1 1 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 5.000s 62.900us 1 1 100.00
entropy_src_sec_cm 5.000s 173.288us 1 1 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 5.000s 62.900us 1 1 100.00
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 5.000s 134.695us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 5.000s 479.303us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 15.000s 632.587us 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 18 22 81.82

Failure Buckets