HMAC Simulation Results

Monday April 14 2025 20:20:50 UTC

GitHub Revision: 71732d1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 7.710s 2.115ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.760s 37.798us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.730s 34.922us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 9.280s 704.912us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 6.890s 326.767us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 21.795m 173.179ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.730s 34.922us 1 1 100.00
hmac_csr_aliasing 6.890s 326.767us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 6.620s 363.913us 1 1 100.00
V2 back_pressure hmac_back_pressure 5.900s 263.914us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 9.350s 381.228us 1 1 100.00
hmac_test_sha384_vectors 6.198m 48.245ms 1 1 100.00
hmac_test_sha512_vectors 5.756m 82.988ms 1 1 100.00
hmac_test_hmac256_vectors 6.690s 699.200us 1 1 100.00
hmac_test_hmac384_vectors 14.160s 2.776ms 1 1 100.00
hmac_test_hmac512_vectors 9.420s 263.327us 1 1 100.00
V2 burst_wr hmac_burst_wr 10.340s 2.259ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 14.750m 6.537ms 1 1 100.00
V2 error hmac_error 52.140s 6.890ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.323m 29.992ms 1 1 100.00
V2 save_and_restore hmac_smoke 7.710s 2.115ms 1 1 100.00
hmac_long_msg 6.620s 363.913us 1 1 100.00
hmac_back_pressure 5.900s 263.914us 1 1 100.00
hmac_datapath_stress 14.750m 6.537ms 1 1 100.00
hmac_burst_wr 10.340s 2.259ms 1 1 100.00
hmac_stress_all 47.770s 1.354ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 7.710s 2.115ms 1 1 100.00
hmac_long_msg 6.620s 363.913us 1 1 100.00
hmac_back_pressure 5.900s 263.914us 1 1 100.00
hmac_datapath_stress 14.750m 6.537ms 1 1 100.00
hmac_wipe_secret 1.323m 29.992ms 1 1 100.00
hmac_test_sha256_vectors 9.350s 381.228us 1 1 100.00
hmac_test_sha384_vectors 6.198m 48.245ms 1 1 100.00
hmac_test_sha512_vectors 5.756m 82.988ms 1 1 100.00
hmac_test_hmac256_vectors 6.690s 699.200us 1 1 100.00
hmac_test_hmac384_vectors 14.160s 2.776ms 1 1 100.00
hmac_test_hmac512_vectors 9.420s 263.327us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 7.710s 2.115ms 1 1 100.00
hmac_long_msg 6.620s 363.913us 1 1 100.00
hmac_back_pressure 5.900s 263.914us 1 1 100.00
hmac_datapath_stress 14.750m 6.537ms 1 1 100.00
hmac_burst_wr 10.340s 2.259ms 1 1 100.00
hmac_error 52.140s 6.890ms 1 1 100.00
hmac_wipe_secret 1.323m 29.992ms 1 1 100.00
hmac_test_sha256_vectors 9.350s 381.228us 1 1 100.00
hmac_test_sha384_vectors 6.198m 48.245ms 1 1 100.00
hmac_test_sha512_vectors 5.756m 82.988ms 1 1 100.00
hmac_test_hmac256_vectors 6.690s 699.200us 1 1 100.00
hmac_test_hmac384_vectors 14.160s 2.776ms 1 1 100.00
hmac_test_hmac512_vectors 9.420s 263.327us 1 1 100.00
hmac_stress_all 47.770s 1.354ms 1 1 100.00
V2 stress_all hmac_stress_all 47.770s 1.354ms 1 1 100.00
V2 alert_test hmac_alert_test 1.930s 14.902us 1 1 100.00
V2 intr_test hmac_intr_test 1.380s 37.689us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.630s 386.651us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.630s 386.651us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.760s 37.798us 1 1 100.00
hmac_csr_rw 1.730s 34.922us 1 1 100.00
hmac_csr_aliasing 6.890s 326.767us 1 1 100.00
hmac_same_csr_outstanding 2.660s 403.131us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.760s 37.798us 1 1 100.00
hmac_csr_rw 1.730s 34.922us 1 1 100.00
hmac_csr_aliasing 6.890s 326.767us 1 1 100.00
hmac_same_csr_outstanding 2.660s 403.131us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.930s 34.711us 1 1 100.00
hmac_tl_intg_err 4.530s 202.299us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 4.530s 202.299us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 7.710s 2.115ms 1 1 100.00
V3 stress_reset hmac_stress_reset 2.210s 53.455us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 2.745m 11.724ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 4.270s 1.066ms 1 1 100.00
TOTAL 28 28 100.00