I2C Simulation Results

Monday April 14 2025 20:20:50 UTC

GitHub Revision: `71732d1`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	23.130s	7.644ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	5.940s	2.854ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.560s	25.374us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.540s	19.311us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.810s	679.927us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.260s	171.483us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.720s	101.658us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.540s	19.311us	1	1	100.00
		i2c_csr_aliasing	2.260s	171.483us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.000s	88.470us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	7.061m	9.097ms	1	1	100.00
V2	host_maxperf	i2c_host_perf	23.400s	7.102ms	1	1	100.00
V2	host_override	i2c_host_override	1.630s	49.772us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	59.650s	5.082ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	33.350s	3.438ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.050s	110.075us	1	1	100.00
		i2c_host_fifo_fmt_empty	10.540s	621.516us	1	1	100.00
		i2c_host_fifo_reset_rx	8.680s	1.028ms	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	29.470s	4.215ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	7.040s	554.654us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.130s	129.615us	0	1	0.00
V2	target_glitch	i2c_target_glitch	7.900s	2.546ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	3.053m	93.090ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.730s	536.400us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	11.070s	1.865ms	1	1	100.00
		i2c_target_intr_smoke	5.670s	5.940ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.810s	142.683us	1	1	100.00
		i2c_target_fifo_reset_tx	1.820s	179.213us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	1.980m	68.148ms	1	1	100.00
		i2c_target_stress_rd	11.070s	1.865ms	1	1	100.00
		i2c_target_intr_stress_wr	11.410s	2.364ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.000s	4.827ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	4.110s	1.147ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.080s	888.372us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.650s	1.273ms	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.300s	1.302ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.850s	169.640us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	23.400s	7.102ms	1	1	100.00
		i2c_host_perf_precise	2.290s	262.135us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	7.040s	554.654us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.010s	65.252us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.660s	948.141us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.620s	468.788us	1	1	100.00
		i2c_target_nack_txstretch	2.050s	881.886us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	9.790s	342.755us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.320s	1.502ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.450s	45.836us	1	1	100.00
V2	intr_test	i2c_intr_test	1.530s	67.349us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.610s	54.304us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.610s	54.304us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.560s	25.374us	1	1	100.00
		i2c_csr_rw	1.540s	19.311us	1	1	100.00
		i2c_csr_aliasing	2.260s	171.483us	1	1	100.00
		i2c_same_csr_outstanding	1.770s	39.975us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.560s	25.374us	1	1	100.00
		i2c_csr_rw	1.540s	19.311us	1	1	100.00
		i2c_csr_aliasing	2.260s	171.483us	1	1	100.00
		i2c_same_csr_outstanding	1.770s	39.975us	1	1	100.00
V2		TOTAL			36	38	94.74
V2S	tl_intg_err	i2c_tl_intg_err	2.050s	906.390us	1	1	100.00
		i2c_sec_cm	1.660s	147.380us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.050s	906.390us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	20.860s	2.317ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.760s	395.960us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	9.930s	3.259ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			45	50	90.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:907) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.28569351346178264600530705189703060599709512496378571673051466972261264368481
    Line 87, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2316999535 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2316999535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.54623426266903177246186909834840457402208029198155323151152183178029445913503
    Line 86, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3259233658 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3259233658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.88512721991515822642874341755714094186303874465910199319123625530646292005161
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 395959693 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 395959693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

Test i2c_host_mode_toggle has 1 failures.

0.i2c_host_mode_toggle.69598305515747260177641565028724895385019422299765007865084036120658353096903
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 129615158 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @29593

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:
- Test i2c_target_nack_txstretch has 1 failures.
  - 0.i2c_target_nack_txstretch.106803138308452210706439502367122069042056517394372638747371429182800581259252
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 881885678 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 881885678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```