KEYMGR Simulation Results

Monday April 14 2025 20:20:50 UTC

GitHub Revision: 71732d1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	23.670s	2.338ms	1	1	100.00
V1	random	keymgr_random	4.120s	629.064us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.610s	189.543us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.790s	19.704us	0	1	0.00
V1	csr_bit_bash	keymgr_csr_bit_bash	9.480s	260.661us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	7.240s	249.225us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.780s	72.464us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.790s	19.704us	0	1	0.00
		keymgr_csr_aliasing	7.240s	249.225us	1	1	100.00
V1		TOTAL			6	7	85.71
V2	cfgen_during_op	keymgr_cfg_regwen	8.360s	400.439us	1	1	100.00
V2	sideload	keymgr_sideload	2.330s	24.145us	1	1	100.00
		keymgr_sideload_kmac	2.930s	64.400us	1	1	100.00
		keymgr_sideload_aes	17.070s	2.293ms	1	1	100.00
		keymgr_sideload_otbn	2.630s	33.537us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.670s	121.040us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	2.400s	92.741us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.740s	50.842us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	2.730s	149.205us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	3.160s	142.730us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.470s	201.664us	1	1	100.00
V2	stress_all	keymgr_stress_all	28.410s	4.881ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.710s	54.297us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.580s	97.001us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.650s	74.057us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.650s	74.057us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.610s	189.543us	1	1	100.00
		keymgr_csr_rw	1.790s	19.704us	0	1	0.00
		keymgr_csr_aliasing	7.240s	249.225us	1	1	100.00
		keymgr_same_csr_outstanding	2.300s	67.740us	0	1	0.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.610s	189.543us	1	1	100.00
		keymgr_csr_rw	1.790s	19.704us	0	1	0.00
		keymgr_csr_aliasing	7.240s	249.225us	1	1	100.00
		keymgr_same_csr_outstanding	2.300s	67.740us	0	1	0.00
V2		TOTAL			15	16	93.75
V2S	sec_cm_additional_check	keymgr_sec_cm	6.130s	240.726us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	6.130s	240.726us	1	1	100.00
		keymgr_tl_intg_err	4.760s	333.958us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.300s	385.517us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.300s	385.517us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.300s	385.517us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.300s	385.517us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	5.110s	112.790us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	6.130s	240.726us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	6.130s	240.726us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	4.760s	333.958us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.300s	385.517us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	8.360s	400.439us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	4.120s	629.064us	1	1	100.00
		keymgr_csr_rw	1.790s	19.704us	0	1	0.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	4.120s	629.064us	1	1	100.00
		keymgr_csr_rw	1.790s	19.704us	0	1	0.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	4.120s	629.064us	1	1	100.00
		keymgr_csr_rw	1.790s	19.704us	0	1	0.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	2.400s	92.741us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	3.160s	142.730us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	3.160s	142.730us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	4.120s	629.064us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.440s	37.425us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	6.130s	240.726us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	6.130s	240.726us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	6.130s	240.726us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	2.810s	84.109us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	2.400s	92.741us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	6.130s	240.726us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	6.130s	240.726us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	6.130s	240.726us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	2.810s	84.109us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	2.810s	84.109us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	6.130s	240.726us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	2.810s	84.109us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	6.130s	240.726us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	2.810s	84.109us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	8.180s	1.683ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			27	30	90.00

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

  • Test keymgr_csr_rw has 1 failures.

    • 0.keymgr_csr_rw.958926106377636197837225210508718630695803837368163165531095442705681806470
      Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[19] & 'hffffffff)))'
        UVM_ERROR @  19703681 ps: (keymgr_csr_assert_fpv.sv:461) [ASSERT FAILED] attest_sw_binding_6_rd_A
        UVM_INFO @  19703681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_same_csr_outstanding has 1 failures.

    • 0.keymgr_same_csr_outstanding.71612016235680482246397327261810048099489516932736765708769534035777710422497
      Line 79, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[7] & 'hffffffff)))'
        UVM_ERROR @  67740357 ps: (keymgr_csr_assert_fpv.sv:401) [ASSERT FAILED] sealing_sw_binding_2_rd_A
        UVM_INFO @  67740357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:907) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 0.keymgr_stress_all_with_rand_reset.11341665990569713656353916954319097912651970546727565167483088723133192445416
      Line 972, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1683467198 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1683467198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---