KMAC/MASKED Simulation Results

Monday April 14 2025 20:20:50 UTC

GitHub Revision: 71732d1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	47.400s	2.683ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.810s	94.350us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.780s	24.502us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	10.970s	354.618us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.190s	863.948us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.500s	125.511us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.780s	24.502us	1	1	100.00
		kmac_csr_aliasing	6.190s	863.948us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.780s	22.579us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.040s	26.739us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	23.032m	391.616ms	1	1	100.00
V2	burst_write	kmac_burst_write	10.098m	15.796ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	22.838m	18.986ms	1	1	100.00
		kmac_test_vectors_sha3_256	27.123m	60.481ms	1	1	100.00
		kmac_test_vectors_sha3_384	22.568m	46.756ms	1	1	100.00
		kmac_test_vectors_sha3_512	16.320s	3.989ms	1	1	100.00
		kmac_test_vectors_shake_128	2.764m	10.573ms	1	1	100.00
		kmac_test_vectors_shake_256	5.350m	18.812ms	1	1	100.00
		kmac_test_vectors_kmac	2.770s	124.614us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.970s	72.466us	1	1	100.00
V2	sideload	kmac_sideload	1.401m	5.567ms	1	1	100.00
V2	app	kmac_app	1.043m	3.286ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.904m	37.788ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.002m	40.573ms	1	1	100.00
V2	error	kmac_error	3.743m	14.326ms	1	1	100.00
V2	key_error	kmac_key_error	16.340s	19.256ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	7.630s	908.939us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.840s	41.838us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.890s	33.726us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	29.970s	22.857ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.070s	141.887us	1	1	100.00
V2	stress_all	kmac_stress_all	17.272m	18.969ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.820s	15.579us	1	1	100.00
V2	alert_test	kmac_alert_test	1.660s	19.787us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.680s	57.570us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.680s	57.570us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.810s	94.350us	1	1	100.00
		kmac_csr_rw	1.780s	24.502us	1	1	100.00
		kmac_csr_aliasing	6.190s	863.948us	1	1	100.00
		kmac_same_csr_outstanding	2.770s	40.240us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.810s	94.350us	1	1	100.00
		kmac_csr_rw	1.780s	24.502us	1	1	100.00
		kmac_csr_aliasing	6.190s	863.948us	1	1	100.00
		kmac_same_csr_outstanding	2.770s	40.240us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.000s	409.158us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.000s	409.158us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.000s	409.158us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.000s	409.158us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.470s	115.944us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	34.260s	3.784ms	1	1	100.00
		kmac_tl_intg_err	1.780s	14.819us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.780s	14.819us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.070s	141.887us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	47.400s	2.683ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.401m	5.567ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.000s	409.158us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	34.260s	3.784ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	34.260s	3.784ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	34.260s	3.784ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	47.400s	2.683ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.070s	141.887us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	34.260s	3.784ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.406m	17.514ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	47.400s	2.683ms	1	1	100.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.412m	24.141ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			38	40	95.00

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.18095477126837422888505200158381178674405049608767667284825878375552719677943
      Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[42] & 'hffffffff)))'
        UVM_ERROR @ 115944406 ps: (kmac_csr_assert_fpv.sv:507) [ASSERT FAILED] prefix_3_rd_A
        UVM_INFO @ 115944406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.56259565032795878616522931049159568264517900070008414979106754617838946687534
      Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[39] & 'hffffffff)))'
        UVM_ERROR @  14818980 ps: (kmac_csr_assert_fpv.sv:492) [ASSERT FAILED] prefix_0_rd_A
        UVM_INFO @  14818980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---