KMAC/UNMASKED Simulation Results

Monday April 14 2025 20:20:50 UTC

GitHub Revision: 71732d1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	28.560s	887.865us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.720s	42.057us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.720s	31.579us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	5.870s	156.192us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.110s	1.361ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.120s	46.816us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.720s	31.579us	1	1	100.00
		kmac_csr_aliasing	4.110s	1.361ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.550s	128.995us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.170s	41.210us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	28.771m	106.497ms	1	1	100.00
V2	burst_write	kmac_burst_write	10.802m	161.821ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	22.950s	2.456ms	1	1	100.00
		kmac_test_vectors_sha3_256	28.120s	8.564ms	1	1	100.00
		kmac_test_vectors_sha3_384	16.462m	92.937ms	1	1	100.00
		kmac_test_vectors_sha3_512	12.542m	168.844ms	1	1	100.00
		kmac_test_vectors_shake_128	21.207m	93.602ms	1	1	100.00
		kmac_test_vectors_shake_256	1.435m	25.210ms	1	1	100.00
		kmac_test_vectors_kmac	2.080s	48.711us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.320s	118.142us	1	1	100.00
V2	sideload	kmac_sideload	3.659m	16.558ms	1	1	100.00
V2	app	kmac_app	1.823m	12.108ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.177m	42.494ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	43.170s	9.059ms	1	1	100.00
V2	error	kmac_error	55.250s	7.779ms	1	1	100.00
V2	key_error	kmac_key_error	4.570s	3.259ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.130s	37.742us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	20.870s	1.713ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	11.210s	1.631ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	12.220s	1.689ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.060s	44.740us	1	1	100.00
V2	stress_all	kmac_stress_all	6.646m	67.085ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.590s	19.004us	1	1	100.00
V2	alert_test	kmac_alert_test	1.610s	27.682us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.640s	66.924us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.640s	66.924us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.720s	42.057us	1	1	100.00
		kmac_csr_rw	1.720s	31.579us	1	1	100.00
		kmac_csr_aliasing	4.110s	1.361ms	1	1	100.00
		kmac_same_csr_outstanding	1.900s	27.022us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.720s	42.057us	1	1	100.00
		kmac_csr_rw	1.720s	31.579us	1	1	100.00
		kmac_csr_aliasing	4.110s	1.361ms	1	1	100.00
		kmac_same_csr_outstanding	1.900s	27.022us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.100s	69.185us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.100s	69.185us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.100s	69.185us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.100s	69.185us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.850s	224.036us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	37.250s	4.192ms	1	1	100.00
		kmac_tl_intg_err	1.680s	8.702us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.680s	8.702us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.060s	44.740us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	28.560s	887.865us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.659m	16.558ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.100s	69.185us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	37.250s	4.192ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	37.250s	4.192ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	37.250s	4.192ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	28.560s	887.865us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.060s	44.740us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	37.250s	4.192ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.609m	15.202ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	28.560s	887.865us	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.018m	8.214ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.62340279401710334912986508434115496319511821695249021889351047159112822945308
      Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[42] & 'hffffffff)))'
        UVM_ERROR @   8701671 ps: (kmac_csr_assert_fpv.sv:507) [ASSERT FAILED] prefix_3_rd_A
        UVM_INFO @   8701671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---