OTBN Simulation Results

Monday April 14 2025 20:20:50 UTC

GitHub Revision: `71732d1`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	357.549us	1	1	100.00
V1	single_binary	otbn_single	24.000s	95.363us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	37.283us	1	1	100.00
V1	csr_rw	otbn_csr_rw	7.000s	21.645us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	7.000s	1.119ms	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	14.455us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	7.000s	74.215us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	7.000s	21.645us	1	1	100.00
		otbn_csr_aliasing	5.000s	14.455us	1	1	100.00
V1	mem_walk	otbn_mem_walk	22.000s	1.819ms	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	10.000s	69.865us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	34.000s	261.392us	1	1	100.00
V2	multi_error	otbn_multi_err	40.000s	696.503us	1	1	100.00
V2	back_to_back	otbn_multi	49.000s	333.945us	1	1	100.00
V2	stress_all	otbn_stress_all	19.000s	184.892us	1	1	100.00
V2	lc_escalation	otbn_escalate	8.000s	38.306us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	39.378us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	16.000s	60.721us	1	1	100.00
V2	alert_test	otbn_alert_test	6.000s	30.634us	1	1	100.00
V2	intr_test	otbn_intr_test	5.000s	13.014us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	7.000s	135.516us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	7.000s	135.516us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	37.283us	1	1	100.00
		otbn_csr_rw	7.000s	21.645us	1	1	100.00
		otbn_csr_aliasing	5.000s	14.455us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	26.236us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	37.283us	1	1	100.00
		otbn_csr_rw	7.000s	21.645us	1	1	100.00
		otbn_csr_aliasing	5.000s	14.455us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	26.236us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	9.000s	20.664us	1	1	100.00
		otbn_dmem_err	11.000s	29.197us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	12.000s	39.471us	1	1	100.00
		otbn_controller_ispr_rdata_err	10.000s	52.886us	1	1	100.00
		otbn_mac_bignum_acc_err	10.000s	110.820us	1	1	100.00
		otbn_urnd_err	8.000s	32.551us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	22.158us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	43.009us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	7.000s	54.030us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	5.000s	1.218us	0	1	0.00
		otbn_tl_intg_err	13.000s	81.117us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	6.000s	8.105us	0	1	0.00
V2S	prim_fsm_check	otbn_sec_cm	5.000s	1.218us	0	1	0.00
V2S	prim_count_check	otbn_sec_cm	5.000s	1.218us	0	1	0.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	357.549us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	11.000s	29.197us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	9.000s	20.664us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	13.000s	81.117us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	8.000s	38.306us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	9.000s	20.664us	1	1	100.00
		otbn_dmem_err	11.000s	29.197us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	39.378us	1	1	100.00
		otbn_illegal_mem_acc	9.000s	22.158us	1	1	100.00
		otbn_sec_cm	5.000s	1.218us	0	1	0.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	5.000s	1.218us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	otbn_single	24.000s	95.363us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	9.000s	20.664us	1	1	100.00
		otbn_dmem_err	11.000s	29.197us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	39.378us	1	1	100.00
		otbn_illegal_mem_acc	9.000s	22.158us	1	1	100.00
		otbn_sec_cm	5.000s	1.218us	0	1	0.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	5.000s	1.218us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	8.000s	38.306us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	9.000s	20.664us	1	1	100.00
		otbn_dmem_err	11.000s	29.197us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	39.378us	1	1	100.00
		otbn_illegal_mem_acc	9.000s	22.158us	1	1	100.00
		otbn_sec_cm	5.000s	1.218us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	5.000s	1.218us	0	1	0.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	24.000s	95.363us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	8.000s	13.519us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	58.648us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	22.000s	70.518us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	22.000s	70.518us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	8.000s	58.968us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	5.000s	1.218us	0	1	0.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	5.000s	1.218us	0	1	0.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	9.000s	215.578us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	5.000s	1.218us	0	1	0.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	5.000s	1.218us	0	1	0.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	9.000s	54.175us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	9.000s	54.175us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	13.000s	69.548us	0	1	0.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	24.000s	95.363us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	24.000s	95.363us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	24.000s	95.363us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	49.000s	333.945us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	24.000s	95.363us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	24.000s	95.363us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	8.000s	41.357us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	24.000s	95.363us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	5.000s	1.218us	0	1	0.00
V2S		TOTAL			17	20	85.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	34.000s	170.307us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			37	41	90.24

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:908) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 0.otbn_stress_all_with_rand_reset.69834638352070110915465906386031136556850298989386769434301544103023716809240
    Line 171, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 170307090 ps: (cip_base_vseq.sv:908) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 170307090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:
- Test otbn_sec_wipe_err has 1 failures.
  - 0.otbn_sec_wipe_err.92877457802729473981770426225309537324802113187803689822731041271971076782292
    Line 113, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log
```
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 69547718 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  69547718 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  69547718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 1 failures:
- Test otbn_passthru_mem_tl_intg_err has 1 failures.
  - 0.otbn_passthru_mem_tl_intg_err.56879529755293723070802974514004457540916493223879178399774643067337018252034
    Line 87, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @   8104757 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @   8104757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 1 failures:

Test otbn_sec_cm has 1 failures.

0.otbn_sec_cm.25313791563743061109993213080341719516416448847197084339769178855469885588234
Line 83, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 1218008 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 1218008 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
  UVM_ERROR @   1218008 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
  UVM_INFO @   1218008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---