ROM_CTRL/32KB Simulation Results

Monday April 14 2025 20:20:50 UTC

GitHub Revision: 71732d1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 5.160s 975.187us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 6.300s 172.417us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 4.430s 130.458us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 4.890s 385.079us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.160s 210.003us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 5.030s 302.066us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 4.430s 130.458us 1 1 100.00
rom_ctrl_csr_aliasing 4.160s 210.003us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 5.110s 130.944us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 4.050s 207.106us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 6.290s 144.981us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 11.420s 328.155us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 7.710s 230.511us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 6.080s 2.765ms 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 8.830s 202.381us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 8.830s 202.381us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 6.300s 172.417us 1 1 100.00
rom_ctrl_csr_rw 4.430s 130.458us 1 1 100.00
rom_ctrl_csr_aliasing 4.160s 210.003us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.670s 168.701us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 6.300s 172.417us 1 1 100.00
rom_ctrl_csr_rw 4.430s 130.458us 1 1 100.00
rom_ctrl_csr_aliasing 4.160s 210.003us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.670s 168.701us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 50.940s 6.043ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 21.540s 831.412us 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 3.075m 1.063ms 1 1 100.00
rom_ctrl_tl_intg_err 23.210s 345.166us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 3.075m 1.063ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 3.075m 1.063ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 50.940s 6.043ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 50.940s 6.043ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 50.940s 6.043ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 50.940s 6.043ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 50.940s 6.043ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 3.075m 1.063ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 3.075m 1.063ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 5.160s 975.187us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 5.160s 975.187us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 5.160s 975.187us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 23.210s 345.166us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 50.940s 6.043ms 1 1 100.00
rom_ctrl_kmac_err_chk 7.710s 230.511us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 50.940s 6.043ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 50.940s 6.043ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 50.940s 6.043ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 21.540s 831.412us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 3.075m 1.063ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.117m 17.904ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00