ROM_CTRL/64KB Simulation Results

Monday April 14 2025 20:20:50 UTC

GitHub Revision: 71732d1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 8.600s 297.281us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 9.690s 1.083ms 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 6.120s 207.089us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.580s 2.101ms 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 7.400s 291.056us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.910s 215.155us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 6.120s 207.089us 1 1 100.00
rom_ctrl_csr_aliasing 7.400s 291.056us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 6.540s 214.605us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 6.770s 1.070ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 7.120s 393.895us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 20.560s 855.564us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 15.720s 550.650us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 9.250s 1.145ms 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 9.610s 274.213us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 9.610s 274.213us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 9.690s 1.083ms 1 1 100.00
rom_ctrl_csr_rw 6.120s 207.089us 1 1 100.00
rom_ctrl_csr_aliasing 7.400s 291.056us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.550s 1.131ms 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 9.690s 1.083ms 1 1 100.00
rom_ctrl_csr_rw 6.120s 207.089us 1 1 100.00
rom_ctrl_csr_aliasing 7.400s 291.056us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.550s 1.131ms 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.905m 2.679ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 25.540s 754.466us 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.596m 1.752ms 1 1 100.00
rom_ctrl_tl_intg_err 36.430s 299.398us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.596m 1.752ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.596m 1.752ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.905m 2.679ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.905m 2.679ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.905m 2.679ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.905m 2.679ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.905m 2.679ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.596m 1.752ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.596m 1.752ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 8.600s 297.281us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 8.600s 297.281us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 8.600s 297.281us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 36.430s 299.398us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.905m 2.679ms 1 1 100.00
rom_ctrl_kmac_err_chk 15.720s 550.650us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.905m 2.679ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.905m 2.679ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.905m 2.679ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 25.540s 754.466us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.596m 1.752ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 2.472m 9.503ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00