RV_DM/USE_JTAG_INTERFACE Simulation Results

Monday April 14 2025 20:20:50 UTC

GitHub Revision: 71732d1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 2.970s 2.590ms 1 1 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 4.200s 1.339ms 1 1 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 1.810s 148.291us 1 1 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 8.830s 7.428ms 1 1 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 1.750s 324.076us 1 1 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 4.380s 2.892ms 1 1 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 4.220s 3.003ms 1 1 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 29.830s 37.015ms 1 1 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 1.912m 117.642ms 1 1 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 2.760s 1.250ms 1 1 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 1.970s 288.184us 1 1 100.00
V1 cmderr_exception rv_dm_cmderr_exception 1.860s 446.369us 1 1 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 1.730s 356.749us 1 1 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.790s 142.284us 1 1 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 1.580s 82.983us 1 1 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.730s 101.549us 1 1 100.00
V1 halt_resume rv_dm_halt_resume_whereto 1.860s 183.249us 1 1 100.00
V1 progbuf_busy rv_dm_cmderr_busy 2.760s 1.250ms 1 1 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 2.180s 109.224us 1 1 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 1.810s 272.516us 1 1 100.00
V1 progbuf_exception rv_dm_cmderr_exception 1.860s 446.369us 1 1 100.00
V1 rom_read_access rv_dm_rom_read_access 1.840s 89.962us 1 1 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.370s 73.879us 1 1 100.00
V1 csr_rw rv_dm_csr_rw 2.060s 108.007us 1 1 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 25.400s 3.847ms 1 1 100.00
V1 csr_aliasing rv_dm_csr_aliasing 54.350s 68.036ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 1.730s 57.445us 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 54.350s 68.036ms 1 1 100.00
rv_dm_csr_rw 2.060s 108.007us 1 1 100.00
V1 mem_walk rv_dm_mem_walk 1.580s 67.568us 1 1 100.00
V1 mem_partial_access rv_dm_mem_partial_access 1.800s 142.118us 1 1 100.00
V1 TOTAL 26 27 96.30
V2 idcode rv_dm_smoke 2.970s 2.590ms 1 1 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 2.940s 723.011us 1 1 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.690s 149.355us 1 1 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 1.670s 82.088us 1 1 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 4.340s 1.488ms 1 1 100.00
V2 sba rv_dm_sba_tl_access 2.220s 2.667ms 1 1 100.00
rv_dm_delayed_resp_sba_tl_access 1.650s 45.623us 0 1 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 3.950s 4.951ms 1 1 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 2.850s 1.276ms 0 1 0.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 2.030s 83.203us 1 1 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 2.330s 1.885ms 1 1 100.00
V2 ndmreset_req rv_dm_ndmreset_req 1.940s 231.772us 1 1 100.00
V2 hart_unavail rv_dm_hart_unavail 1.590s 133.199us 1 1 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 11.080s 5.384ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 1.720s 120.485us 0 1 0.00
V2 hartsel_warl rv_dm_hartsel_warl 1.920s 184.262us 1 1 100.00
V2 stress_all rv_dm_stress_all 4.530s 4.894ms 1 1 100.00
V2 alert_test rv_dm_alert_test 1.620s 52.615us 1 1 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 1.700s 36.913us 0 1 0.00
V2 tl_d_illegal_access rv_dm_tl_errors 1.700s 36.913us 0 1 0.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 54.350s 68.036ms 1 1 100.00
rv_dm_csr_hw_reset 2.370s 73.879us 1 1 100.00
rv_dm_csr_rw 2.060s 108.007us 1 1 100.00
rv_dm_same_csr_outstanding 8.380s 175.214us 1 1 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 54.350s 68.036ms 1 1 100.00
rv_dm_csr_hw_reset 2.370s 73.879us 1 1 100.00
rv_dm_csr_rw 2.060s 108.007us 1 1 100.00
rv_dm_same_csr_outstanding 8.380s 175.214us 1 1 100.00
V2 TOTAL 15 19 78.95
V2S tl_intg_err rv_dm_sec_cm 4.270s 1.323ms 1 1 100.00
rv_dm_tl_intg_err 7.140s 700.752us 1 1 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 7.140s 700.752us 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 2.330s 1.885ms 1 1 100.00
rv_dm_debug_disabled 1.840s 50.070us 1 1 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 2.330s 1.885ms 1 1 100.00
rv_dm_debug_disabled 1.840s 50.070us 1 1 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 2.970s 2.590ms 1 1 100.00
V2S sec_cm_dm_en_ctrl_lc_gated rv_dm_buffered_enable 1.740s 180.071us 1 1 100.00
V2S sec_cm_sba_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.640s 117.979us 1 1 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.640s 117.979us 1 1 100.00
V2S sec_cm_exec_ctrl_mubi rv_dm_buffered_enable 1.740s 180.071us 1 1 100.00
V2S TOTAL 5 5 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 1.680s 97.529us 0 1 0.00
V3 TOTAL 0 1 0.00
Unmapped tests rv_dm_scanmode 1.460s 11.666us 1 1 100.00
TOTAL 47 53 88.68

Failure Buckets