SPI_DEVICE/1R1W Simulation Results

Monday April 14 2025 20:20:50 UTC

GitHub Revision: 71732d1

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	2.330m	94.372ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.960s	41.396us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.740s	35.025us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	17.770s	1.584ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	10.460s	856.738us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.200s	192.555us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.740s	35.025us	1	1	100.00
		spi_device_csr_aliasing	10.460s	856.738us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.500s	12.782us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.720s	53.430us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.850s	14.634us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.430s	4.622us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.460s	2.512us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.890s	131.784us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.890s	131.784us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	1.530s	12.847us	1	1	100.00
		spi_device_tpm_sts_read	1.740s	18.290us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	3.770s	254.892us	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	15.670s	16.586ms	1	1	100.00
		spi_device_flash_all	1.212m	16.713ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	5.780s	1.474ms	1	1	100.00
		spi_device_flash_all	1.212m	16.713ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	5.780s	1.474ms	1	1	100.00
		spi_device_flash_all	1.212m	16.713ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.212m	16.713ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	2.580s	32.386us	1	1	100.00
		spi_device_flash_all	1.212m	16.713ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	2.580s	32.386us	1	1	100.00
		spi_device_flash_all	1.212m	16.713ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	2.580s	32.386us	1	1	100.00
		spi_device_flash_all	1.212m	16.713ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	2.580s	32.386us	1	1	100.00
		spi_device_flash_all	1.212m	16.713ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	2.580s	32.386us	1	1	100.00
		spi_device_flash_all	1.212m	16.713ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	2.440s	373.690us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	44.870s	29.917ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	44.870s	29.917ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	44.870s	29.917ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	6.610s	277.295us	1	1	100.00
		spi_device_read_buffer_direct	4.220s	190.187us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	44.870s	29.917ms	1	1	100.00
		spi_device_flash_all	1.212m	16.713ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.212m	16.713ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.212m	16.713ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.100s	96.616us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.100s	96.616us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	2.330m	94.372ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.495m	15.817ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.961m	52.304ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.980s	15.231us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.750s	11.941us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.300s	31.887us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.300s	31.887us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.960s	41.396us	1	1	100.00
		spi_device_csr_rw	1.740s	35.025us	1	1	100.00
		spi_device_csr_aliasing	10.460s	856.738us	1	1	100.00
		spi_device_same_csr_outstanding	2.300s	117.825us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.960s	41.396us	1	1	100.00
		spi_device_csr_rw	1.740s	35.025us	1	1	100.00
		spi_device_csr_aliasing	10.460s	856.738us	1	1	100.00
		spi_device_same_csr_outstanding	2.300s	117.825us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.140s	258.406us	1	1	100.00
		spi_device_tl_intg_err	17.040s	868.228us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	17.040s	868.228us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	25.220s	2.900ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.17546098372432825447849678379097941182677067988065636504311134266497020134522
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   3518598 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[31])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   3518598 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   3518598 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[927])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.104109494083175447485165979370138702423546909683594175103839386927402073065073
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1945351 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1945351 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   2018351 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xdc7173 [110111000111000101110011] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   2018351 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0xdc7173 [110111000111000101110011] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])